Ferroelectric Gate-Coupled Memory Circuit for Lower Leakage
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Solution Overview
Problem
Current memory architectures suffer from large leakage currents, which deteriorate data storage performance in semiconductor memory devices.
Innovation Solution
A memory device comprising a storage transistor, a variable capacitance device, and a control transistor, where the variable capacitance device is electrically connected to the gate of the storage transistor, and the control transistor is connected in series, utilizing a ferroelectric layer for improved storage characteristics, along with specific contact plugs and wires for enhanced connectivity and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory architecture is used, then device simplicity is maintained, but large leakage currents occur deteriorating data storage
Solution Approach 1:
The memory device is segmented into distinct functional components: a storage transistor for data holding, a variable capacitance device for state control, and a control transistor for operation management. This segmentation allows each component to be optimized independently, with the variable capacitance device specifically addressing leakage current issues while the storage transistor maintains data storage function.
Solution Approach 2:
A variable capacitance device is introduced as an intermediary element between the control transistor and the storage transistor gate. This intermediary component modulates the electric field at the storage transistor gate through capacitance variation, enabling precise control of the storage state while minimizing direct current paths that would cause leakage.
2Reliability
If variable capacitance device is added to reduce leakage, then data storage is improved, but device complexity increases
Solution Approach 1:
The variable capacitance device serves multiple functions simultaneously: it controls the storage state by modulating gate voltage, it reduces leakage currents through capacitance modulation, and it enables non-volatile storage characteristics. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The control transistor and variable capacitance device are merged into a integrated control structure where the variable capacitance device is electrically connected to the storage transistor gate through the control transistor. This merging allows coordinated operation of control and storage functions within a unified device architecture, reducing the need for separate external control circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage currents, enhancing data storage and improving the signal-to-noise ratio in memory circuits, thereby improving data storage performance.
Implementation Method 1
the variable capacitance layer is a ferroelectric layer
Data Source
AI summary
The present disclosure provides a memory circuit, a memory device and an operating method of the memory device. The memory device includes a storage transistor, a variable capacitance device and a control transistor. The variable capacitance device is electrically connected to the gate of the storage transistor, and the control transistor is connected to the storage transistor in series.