Gate-Coupled SCR for ESD Protection in Semiconductor Devices
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Solution Overview
Problem
Conventional silicon-controlled rectifiers (SCRs) for electrostatic discharge (ESD) protection have high trigger voltage, low holding voltage, and slow turn-on speed, which can lead to damage and failure of integrated circuits.
Innovation Solution
A semiconductor device with a gate-coupled SCR structure, featuring a substrate with N-well and P-well regions, heavily-doped regions, and an insulating layer, forming an embedded field-effect transistor, which reduces trigger voltage and increases holding voltage for effective ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional SCR structure is used for ESD protection, then the device can provide ESD protection function, but the trigger voltage is high and turn-on speed is slow
Solution Approach 1:
The SCR structure is segmented by introducing a gate electrode that divides the control function, allowing independent optimization of trigger voltage and holding voltage characteristics. The gate electrode separates the trigger path from the holding path, enabling the trigger voltage to be reduced while maintaining high holding voltage.
Solution Approach 2:
The gate electrode acts as an intermediary element that controls the turn-on process of the SCR. By applying a gate voltage, the trigger voltage is reduced and turn-on speed is accelerated without affecting the inherent holding voltage characteristic of the SCR structure.
2Reliability
If a conventional SCR structure is used for ESD protection, then the device can provide ESD protection function, but the trigger voltage is high
Solution Approach 1:
The SCR structure is segmented by introducing a gate electrode that divides the control function, allowing independent optimization of trigger voltage and holding voltage characteristics. The gate electrode separates the trigger path from the holding path, enabling the trigger voltage to be reduced while maintaining high holding voltage.
Solution Approach 2:
The gate electrode acts as an intermediary element that controls the turn-on process of the SCR. By applying a gate voltage, the trigger voltage is reduced and turn-on speed is accelerated without affecting the inherent holding voltage characteristic of the SCR structure.
3Reliability
If a conventional SCR structure is used for ESD protection, then the device can provide ESD protection function, but the holding voltage is low
Solution Approach 1:
Different regions of the device are given different doping concentrations to achieve local optimization. The heavily-doped regions are localized at specific positions to enhance the holding voltage characteristic without affecting the overall ESD protection function. This local quality enhancement allows the holding voltage to be maintained at high levels.
4Speed
If the SCR is designed to reduce trigger voltage, then turn-on speed improves, but holding voltage may decrease
Solution Approach 1:
The SCR structure is segmented by introducing a gate electrode that divides the control function, allowing independent optimization of trigger voltage and holding voltage characteristics. The gate electrode separates the trigger path from the holding path, enabling the trigger voltage to be reduced while maintaining high holding voltage.
Solution Approach 2:
Different regions of the device are given different doping concentrations to achieve local optimization. The heavily-doped regions are localized at specific positions to enhance the holding voltage characteristic without affecting the overall ESD protection function. This local quality enhancement allows the holding voltage to be maintained at high levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device effectively reduces the trigger voltage and turn-on time during ESD events, preventing damage to integrated circuits by maintaining a high holding voltage during normal operation and switching to a low-resistance state during ESD occurrences.
Implementation Method 1
The gate electrode, the insulating layer, the channel region, and the first and second heavily-doped regions form an embedded field-effect transistor (FET)
Data Source
AI summary
A semiconductor device includes a substrate, and first and second wells formed in the substrate. The first well has a first conductivity type. The second well has a second conductivity type different than the first conductivity type. The device includes a first heavily-doped region having the first conductivity type and a second heavily-doped region having the first conductivity type. A portion of the first heavily-doped region is formed in the first well. The second heavily-doped region is formed in the second well. The device also includes an insulating layer formed over a channel region of the substrate between the first and second heavily-doped regions, and a gate electrode formed over the insulating layer. The device further includes a terminal for coupling to a circuit being protected, and a switching circuit coupled between the terminal and the first heavily-doped region, and between the terminal and the gate electrode.