Semiconductor Gate Cross-Coupling Pattern for Parasitic Capacitance Reduction
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Solution Overview
Problem
Semiconductor devices face challenges in achieving low parasitic capacitance and high-speed operation due to the limitations of existing cross-coupling structures in conductive patterns and connection patterns.
Innovation Solution
A semiconductor device with a cross-coupling structure that includes a first and second gate structure, a cross-coupling pattern, a first contact plug, and a second contact plug, where the cross-coupling pattern contacts the sidewalls of the gate structures and connects them electrically, with the contact plugs directly contacting the gate structures and the cross-coupling pattern, and an insulation layer pattern surrounding the cross-coupling pattern to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional cross-coupling structures are used to connect conductive patterns, then electrical connection is achieved, but parasitic capacitance increases and operating speed decreases
Solution Approach 1:
The cross-coupling pattern transitions from a planar two-dimensional connection to a three-dimensional structure that contacts sidewalls of gate structures. This vertical/diagonal dimensionality change reduces the horizontal footprint and overlapping area, thereby decreasing parasitic capacitance while maintaining electrical connectivity between conductive patterns.
Solution Approach 2:
The connection structure is divided into multiple segments: contact plugs at gate ends, cross-coupling patterns connecting sidewalls, and insulation layers separating adjacent structures. This segmentation allows each component to be optimized independently, reducing overall parasitic capacitance while achieving the required electrical connection.
2Reliability
If cross-coupling patterns contact sidewalls of gate structures, then electrical connection is improved, but manufacturing complexity increases
Solution Approach 1:
Gate structures are formed with exposed end portions and sidewalls before the cross-coupling patterns are deposited. Contact plugs are pre-formed at the gate ends to establish initial connection points. This preliminary preparation simplifies the subsequent formation of cross-coupling patterns, as the target contact areas are already defined and accessible.
Solution Approach 2:
Insulation layer patterns are introduced as intermediary elements between the cross-coupling patterns and substrate or adjacent structures. These insulation layers serve as both electrical isolators and structural guides, simplifying the overall device architecture by clearly defining electrical boundaries and reducing direct complexity between conductive elements.
3Reliability
If contact plugs directly contact gate structures and cross-coupling patterns, then connection reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
Gate structures are formed with intentionally exposed end portions and defined sidewalls before contact plug deposition. These exposed features serve as pre-defined alignment targets, allowing contact plugs to be accurately positioned without requiring ultra-precise alignment during the contact formation process itself. The preliminary gate structure acts as a self-aligning template.
Solution Approach 2:
The gate structure's own geometry (exposed ends and sidewalls) serves as the alignment reference for contact plug placement. Rather than requiring external alignment marks or complex positioning systems, the structure itself provides the necessary geometric cues for accurate contact formation, reducing manufacturing precision requirements.
4Object-generated harmful factors
If top surfaces are made coplanar, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The cross-coupling pattern and contact plugs are formed using the same deposition and planarization processes as the gate structures themselves. This universal process approach allows all structures to be coplanarized simultaneously in a single process flow, reducing overall process complexity despite the added requirement for coplanarity. The same tools and methods serve multiple functions.
Data Source
AI summary
In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. A second gate structure is formed on the substrate, and has a second end portion opposite to the first end portion of the first gate structure in a diagonal direction. A cross-coupling pattern is formed between the first and second gate structure, and electrically connects the first and second gate structures to each other. A first contact plug directly contacts an upper portion of the first end portion of the first gate structure and a first upper sidewall of the cross-coupling pattern. A second contact plug directly contacts an upper portion of the second end portion of the second gate structure and a second upper sidewall of the cross-coupling pattern. In the semiconductor device, a parasitic capacitance due to the cross-coupling structure may decrease.