Power Semiconductor Gate Crossing Geometry for Thermal Stability

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Solution Overview

Problem

Power semiconductor devices with high transconductance face thermal instability and reduced safe operating area (SOA) due to increased risk of thermal runaway, limiting their operational capabilities.

Innovation Solution

The design incorporates a semiconductor substrate with active transistor cells featuring spicular trenches and intersecting gate trenches forming gate crossing regions of different shapes, which reduces the threshold voltage and transconductance, mitigating thermal runaway and expanding the SOA by creating regions with varying temperature coefficients.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the transconductance per chip area is increased to minimize on-state resistance and reduce losses, then the switching performance is improved, but the thermal stability deteriorates and the risk of thermal runaway increases

Engineering Contradiction:
Improveon-state resistance lossesVSAvoidthermal stability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent applies local quality by creating different gate crossing geometries (first type with acute angle, second type with obtuse angle) in different regions of the semiconductor device. This results in local variations of the temperature coefficient ∂ID/∂T, where some regions have positive temperature coefficients and others have negative temperature coefficients. This local differentiation allows the device to maintain high overall transconductance while distributing thermal stress, preventing thermal runaway in high-transconductance areas.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the geometric parameters of the gate crossings (angles, dimensions, orientations) to control the local electrical and thermal characteristics. By varying the gate crossing geometry, the threshold voltage and transconductance are locally adjusted, which in turn modifies the temperature coefficient ∂ID/∂T in different regions. This parameter variation enables the device to operate with high transconductance overall while maintaining thermal stability through regions with negative temperature coefficients.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the transconductance is increased to improve switching speed and reduce losses, then the efficiency is improved, but the safe operating area is reduced due to thermal runaway risk

Engineering Contradiction:
Improveswitching speedVSAvoidsafe operating area
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates regions with different gate crossing types (acute angle vs. obtuse angle) that exhibit different thermal behaviors. Regions with negative temperature coefficients provide thermal stability and expand the safe operating area, while regions with positive temperature coefficients maintain high transconductance for fast switching. This local differentiation allows the device to operate safely across a wider range of conditions while maintaining high productivity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent converts the potentially harmful effect of high transconductance (which causes thermal runaway) into a beneficial distributed structure. By intentionally creating regions with negative temperature coefficients through specific gate crossing geometries, the device uses the same high-transconductance mechanism to provide thermal stabilization, thus converting the harmful thermal runaway tendency into a beneficial self-regulating thermal management system that expands the safe operating area.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If the device operates in saturation mode with high drain-source voltage to limit current, then the protective function is achieved, but the thermal instability increases due to positive temperature coefficient

Engineering Contradiction:
Improveprotective functionVSAvoidthermal stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent implements local quality by distributing different gate crossing types throughout the device, creating regions with negative temperature coefficients that provide thermal stability during saturation mode operation. These stable regions counterbalance the positive temperature coefficient regions, preventing thermal runaway when the device operates at high drain-source voltages for current limiting and protective functions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces a negative feedback mechanism through regions with negative temperature coefficients. When temperature increases in high-transconductance regions, the negative temperature coefficient regions reduce their current conduction, providing a stabilizing feedback effect that prevents thermal runaway. This automatic feedback control enables the device to maintain thermal stability while performing protective functions in saturation mode.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10629595B2Power semiconductor device having different gate crossings, and method for manufacturing thereof
Publication Date: 2020.04.21 INFINEON TECH AUSTRIA AG
  • US10629595B2 patent drawing
  • US10629595B2 patent drawing
  • US10629595B2 patent drawing

AI summary

A power semiconductor device includes a semiconductor substrate having a first side. A plurality of active transistor cells is formed in an active area of the semiconductor substrate. Each of the plurality of active transistor cells includes a spicular trench which extends from the first side into the semiconductor substrate and has a field electrode. A gate electrode structure has a plurality of intersecting gate trenches running between the spicular trenches. The intersecting gate trenches form gate crossing regions of different shape when seen in a plan projection onto the first side of the power semiconductor device.