Gate Current Mirroring in Current Source Converters to Cut Overlap Losses
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Solution Overview
Problem
Current source converters face challenges due to the need for overlapping ON states between switching devices to prevent current interruption, which leads to overvoltage and potential damage, and results in increased Total Harmonic Distortion (THD) and conduction losses.
Innovation Solution
A control circuit for current source converters that reduces the overlapping time between conducting and non-conducting states of power semiconductor switches by using a gate current mirroring circuit and gate pull-down signals to anticipate and manage the switching transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If overlapping time between switching devices is increased to prevent current interruption, then reliability is improved, but Total Harmonic Distortion (THD) increases and conduction losses increase
Solution Approach 1:
The gate current mirroring circuit detects the turning ON state of a switching device in advance and generates a gate pull down signal before the overlapping period ends. This preliminary action allows the other switching device to turn OFF earlier, reducing the overlapping time while ensuring current continuity is maintained until the exact moment needed.
Solution Approach 2:
The gate current mirroring circuit provides real-time feedback on the gate current state of switching devices. By monitoring when a device turns ON through the mirroring circuit, the system can dynamically adjust the turn OFF timing of complementary devices, optimizing the overlapping time to minimize losses while maintaining reliability.
2Reliability
If overlapping time between switching devices is increased to prevent current interruption, then reliability is improved, but Total Harmonic Distortion (THD) increases
Solution Approach 1:
The gate pull down signal is generated in advance by the mirroring circuit when a switching device turns ON, enabling the complementary device to turn OFF before the overlapping period expires. This reduces the effective overlapping time, minimizing THD while maintaining current continuity through the preliminary timing adjustment.
3Loss of energy
If overlapping time is reduced to minimize losses and THD, then efficiency is improved, but risk of current interruption increases
Solution Approach 1:
The gate current mirroring circuit automatically detects when a switching device turns ON and self-generates the gate pull down signal for the complementary device without external intervention. This self-service mechanism ensures the overlapping time is optimized in real-time, minimizing losses while reliably preventing current interruption.
Solution Approach 2:
The patent replaces complex mechanical or external control mechanisms with an electronic gate current mirroring circuit that automatically manages the switching timing. This substitution enables precise, rapid response to switching events, reducing overlapping time effectively while maintaining current continuity through electronic feedback control.
Data Source
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AI summary
Control circuit for a current source converter having a current generator comprising an inductance (2) and having two or more half bridges each half bridge having an upper leg provided with an upper switching device (11, 13) and a lower leg provided with a lower switching device (12, 14), said upper legs switching devices and said lower legs switching devices being controlled by a controller (40) to provide an overlap between an upper leg turning off switching device (11, 13) and an upper leg turning on switching device (13, 11) and to provide an overlap between a lower leg turning on switching device (12, 14) and a lower leg turning off switching device (14, 12) through gate pull up and gate pull down pulse signals to gate drivers buffers (6) of said switching devices, said gate driver circuit comprising: - for each upper leg switching device and each lower leg switching device (11, 12, 13, 14) a gate current mirroring circuit (51) on a source branch of the gate driver buffer (6) of said switching device (11, 12, 13, 14) to provide a gate pull down signal (Gpx, Gpy) upon turning OFF of said switching device, said gate pull down signal (Gpx, Gpy) being connected to a control line (Cl) of a gate buffer (6) of a respective further upper leg switching device or further lower leg switching device (11, 12, 13, 14), - for each upper leg switching device and each lower leg switching device (11, 12, 13, 14) a positive gate command connection path (G+) from a positive gate command output of a pre-driver (7) to provide a reset signal (RSTx, RSTy) for a respective further upper leg switching device and lower leg switching device (11, 12, 13, 14) gate pull down signal.