Gate Cut and Backside Via Layout for Isolated Cell Routing
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Solution Overview
Problem
The challenge in integrated circuits is the efficient formation of semiconductor devices with gate cuts and deep backside vias, which is complicated by the need for electrical isolation and power routing in densely packed memory and logic cells, requiring innovative methods to overcome the limitations of existing fabrication processes.
Innovation Solution
The technique involves forming semiconductor devices with alternating gate cuts and deep backside vias, where dielectric walls and conductive vias extend through the entire thickness of the gate structure, allowing for efficient power and signal routing by separating adjacent devices and providing conductive pathways, using materials like silicon nitride for dielectric walls and tungsten or molybdenum for conductive vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If deep backside vias are formed to extend through the substrate to improve power and signal routing, then routing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the isolation structure into two distinct components: gate cuts that extend through the gate structure, and deep backside vias that extend through the substrate. This segmentation allows each structure to perform its specific function independently - gate cuts provide local isolation at the gate level while deep backside vias provide through-substrate routing paths, thereby improving routing efficiency without excessively complicating the fabrication process
Solution Approach 2:
The patent transitions from two-dimensional planar isolation to three-dimensional vertical structures by forming deep backside vias that extend through the substrate thickness. This dimensional change enables power and signal routing to occur in the vertical dimension, improving routing efficiency by utilizing the third dimension for interconnect paths while maintaining a relatively straightforward fabrication process using standard via formation techniques
2Reliability
If gate cuts are formed to extend through the gate structure to improve electrical isolation, then isolation performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of gate cuts and deep backside vias into a coordinated fabrication sequence where both structures are formed using similar etching and filling processes. The gate cuts extend through the gate structure while deep backside vias extend through the substrate, and both are formed in alternating patterns. This merging of formation processes improves electrical isolation performance while avoiding the need for entirely separate fabrication workflows, thereby maintaining manufacturing simplicity
3Productivity
If alternating gate cuts and deep backside vias are formed to improve power routing, then power distribution efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the power distribution network into alternating gate cuts and deep backside vias that extend through the substrate. This segmentation creates multiple parallel routing paths for power distribution, improving power distribution efficiency by providing redundant and distributed current paths. The alternating pattern ensures uniform power delivery across the device while maintaining a regular, predictable structure that does not excessively increase fabrication complexity
Solution Approach 2:
The patent creates structures that serve multiple functions: the gate cuts provide both local electrical isolation and power routing, while the deep backside vias provide both signal routing and power distribution. This multi-functionality improves power distribution efficiency by having structures that simultaneously perform isolation and routing tasks, thereby reducing the need for separate dedicated power routing structures and avoiding excessive increases in overall device complexity
Data Source
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AI summary
Techniques are provided herein to form semiconductor devices arranged between a gate cut on one side and a deep backside via on the other side. A row of semiconductor devices each include a semiconductor region (102, 104) extending in a first direction between corresponding source or drain regions, and a gate structure (106) extending in a second direction over the semiconductor regions. Each semiconductor device is separated from an adjacent semiconductor device along the second direction by either a gate cut (112) or a deep backside via (114). The gate cut is a dielectric wall that extends through an entire thickness of the gate structure and the deep backside via includes a conductive layer and may further include a dielectric barrier that also extend through at least an entire thickness of the gate structure. Each semiconductor device has a gate cut on one side and a deep backside via on the other side.