Gate Cut Contact Layout for Low-Resistance Source/Drain Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuits scale down, forming source and drain contacts with low contact resistance becomes challenging due to increased density and reduced spacing, leading to difficulties in interconnection and routing of devices.
Innovation Solution
A technique involving the formation of a continuous and monolithic source or drain contact over multiple regions, followed by a gate cut to bifurcate it into separate contacts, with an optional bridge contact to reconnect severed contacts, enhancing contact surface area on both top and side surfaces to reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are packed more densely in a given device layer, then device integration density is improved, but contact resistance increases and interconnection becomes challenging
Solution Approach 1:
The patent extends contacts from traditional planar top-surface-only configuration to include sidewall portions, utilizing the vertical dimension. This three-dimensional contact structure increases the effective contact area without occupying additional lateral space, thereby maintaining high device integration density while reducing contact resistance through enhanced contact area between the contact and source/drain regions.
Solution Approach 2:
The contact is divided into multiple segments: a top surface portion and one or more sidewall portions. This segmentation allows each portion to contribute independently to the total contact area, enabling the contact to wrap around the source/drain region and maximize electrical connection without increasing the lateral footprint of the device.
2Reliability
If contact surface area is increased to reduce contact resistance, then contact resistance decreases, but device capacitance increases
Solution Approach 1:
By transitioning from a two-dimensional planar contact to a three-dimensional contact that includes sidewalls, the patent increases contact area vertically rather than laterally. This dimensional change allows for reduced contact resistance without proportionally increasing the lateral device footprint and associated parasitic capacitance, as the additional contact area is achieved through vertical extension along the sidewalls of the source/drain regions.
3Ease of manufacture
If continuous and monolithic contact is formed over multiple regions, then manufacturing simplicity is improved, but gate isolation becomes challenging
Solution Approach 1:
The continuous contact is segmented by gate cuts that extend through the contact material, dividing it into discrete contacts for adjacent devices. This segmentation achieves proper gate isolation between devices while the contact formation process itself remains relatively simple, as it can be performed as a blanket deposition followed by selective removal or patterning steps that define the final contact regions.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2A~2B
AI summary
An integrated circuit includes a first device (101a), and a laterally adjacent second device (101a). The first device includes a first body of semiconductor material extending laterally from a first source or drain region (130a), a first gate structure on the first body, and a first contact (138a) extending vertically upward from the first source or drain region. The second device includes a second body of semiconductor material extending laterally from a second source or drain region (130b), a second gate structure on the second body, and a second contact (138b) extending vertically upward from the second source or drain region. A gate cut structure (114) including dielectric material is laterally between the first gate structure and the second gate structure, and also laterally between the first contact (138a) and the second contact (138b). A third contact (140) extends laterally from the first contact to the second contact and passes over the gate cut structure.