Gate-Cut and Diffusion Break Integration With Low-Temperature Liners
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Solution Overview
Problem
Conventional methods for forming integrated circuits with non-planar transistors face challenges in integrating gate-cuts and single diffusion break isolation structures, particularly for nanosheet FETs, due to substrate space consumption and difficulty in fabricating gate tucks, which affect device density and performance.
Innovation Solution
A method involving low-temperature fabrication processes forms a sacrificial metal gate and a shared non-sacrificial metal gate, with a single mask defining both single diffusion break and gate-cut footprints, using low-temperature protective liners to minimize thermal damage, and depositing dielectric materials to create isolated transistors with reduced substrate interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-temperature processes are used for forming gate-cuts and single diffusion break isolation, then the isolation structures can be formed, but thermal damage and substrate stress increase
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processes to low-temperature processes (below 400°C, preferably below 300°C). This is achieved by using protective liners that enable low-temperature etching, thereby forming gate-cuts and single diffusion break isolation structures without causing thermal damage to the substrate or previously formed structures.
Solution Approach 2:
The patent introduces protective liners as intermediary layers between the etching process and the substrate/structures. These liners protect sensitive regions from direct exposure to harsh etching conditions, enabling the use of low-temperature processes while still achieving effective isolation. The liners are selectively removed after serving their protective function.
2Manufacturing precision
If separate processes are used for gate-cuts and single diffusion break isolation, then each structure can be formed with precision, but fabrication complexity and time increase
Solution Approach 1:
The patent merges the formation of gate-cuts and single diffusion break isolation structures into a single integrated process step. By using a single mask pattern that defines both the gate-cut regions and the single diffusion break isolation regions, both structures are formed simultaneously through one etching process, thereby reducing fabrication complexity and time while maintaining precision.
Solution Approach 2:
The patent creates a multi-functional mask and etching process that serves multiple purposes: it forms gate-cuts for transistor isolation, creates single diffusion break isolation structures, and defines protective liner removal regions. This universal approach eliminates the need for separate dedicated processes for each structure type.
3Reliability
If substrate space is consumed by isolation structures, then device isolation is achieved, but device density decreases
Solution Approach 1:
The patent applies local quality by forming single diffusion break isolation structures that provide electrical isolation only where specifically needed, rather than using continuous isolation regions. The isolation is localized to break diffusion paths at critical interfaces, minimizing the substrate area consumed while still achieving the necessary device isolation for reliable operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient integration of gate-cuts and single diffusion break isolation in integrated circuits, enhancing device density and performance while minimizing thermal stress, thus improving the fabrication of non-planar transistors like nanosheet FETs.
Implementation Method 1
low-temperature (e.g., less than about 300 degrees Celsius) protective liners... minimizing thermal damage, and depositing dielectric materials
Implementation Method 2
depositing dielectric materials to create isolated transistors
Data Source
AI summary
Embodiments of the invention are directed to a method of fabricating an integrated circuit (IC). The method includes performing fabrication operations to form transistors on a substrate. The fabrication operations include forming a sacrificial metal gate and forming a shared non-sacrificial metal gate. The sacrificial metal gate is recessed to form a sacrificial metal gate, and the shared non-sacrificial metal gate is recessed to form a recessed shared non-sacrificial metal gate. A pattern is formed over the sacrificial metal gate and the recessed shared non-sacrificial metal gate. The pattern defines a single diffusion break footprint over a top surface of the sacrificial metal gate, along with a gate-cut footprint over a central region of a top surface of the recessed shared non-sacrificial metal gate.