Gate Dielectric-Preserving Gate Cut for FinFET Etch Isolation

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Solution Overview

Problem

Conventional gate cutting techniques for integrated circuits, particularly at advanced technology nodes, face challenges in densely packed feature environments, where lateral etching can damage surrounding source/drain features, leading to reduced reliability and yield.

Innovation Solution

The technique involves selectively removing a portion of the gate structure to preserve the gate dielectric, which acts as a barrier during etching, minimizing damage to nearby source/drain features and increasing etching selectivity to protect these critical components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching processes are used to remove gate structures, then gate cutting is achieved, but lateral etching damages surrounding source/drain features

Engineering Contradiction:
Improvegate cutting precisionVSAvoidlateral etching damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

A mandrel structure is introduced as an intermediary element between the etching process and the gate structure. The mandrel serves as a protective barrier that prevents lateral etching from reaching and damaging the source/drain features while allowing the etching process to effectively remove the gate structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The mandrel structure is formed in advance before the etching process. This preliminary action establishes a protective barrier that will prevent harmful lateral etching during the subsequent gate removal process, ensuring source/drain feature integrity from the outset.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If complete gate stack removal is performed, then gate cutting is achieved, but source/drain features are damaged by lateral etching

Engineering Contradiction:
Improvegate cutting efficiencyVSAvoidsource/drain feature integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The mandrel acts as a mediator that enables complete gate stack removal while protecting the source/drain features. It allows the etching process to proceed aggressively for productivity while the mandrel absorbs the lateral etching impact, preventing damage to critical source/drain structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The mandrel structure converts the potentially harmful lateral etching into a beneficial protective mechanism. The same lateral etching that would normally damage source/drain features is redirected to erode the mandrel instead, turning a harmful effect into a protective function.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability and yield of FinFET devices by preventing lateral etching damage to source/drain features, ensuring the integrity of the gate dielectric and maintaining the functionality of the integrated circuit devices.

Implementation Method 1

conventional gate cutting techniques typically implement etching processes that completely (or substantially) remove an entire portion of a gate stack

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS11876013B2Gate dielectric preserving gate cut process
Publication Date: 2024.01.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11876013B2 patent drawing
  • US11876013B2 patent drawing
  • US11876013B2 patent drawing

AI summary

Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.