Gate Cut Structure Layout for Source/Drain Etch Protection
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Solution Overview
Problem
The formation of gate cut structures in semiconductor devices can interfere with existing source or drain regions, leading to undesired etching and integrity issues, particularly in advanced transistor technologies like finFETs and gate-all-around transistors.
Innovation Solution
The formation of gate cut structures is delayed until after the gate structures are formed, using sacrificial fill materials in the source/drain regions, followed by removal of the sacrificial fill and subsequent epitaxial growth of source or drain regions, with dielectric liners on the sidewalls to protect these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate cut structures are formed before source or drain regions, then gate structure formation is simplified, but source or drain regions suffer from undesired etching and integrity issues
Solution Approach 1:
Source or drain regions are formed in advance using sacrificial fill materials before gate cut structures are created. This preliminary formation allows the gate cuts to be made without subsequently damaging the source or drain regions, as they are already in place and protected.
Solution Approach 2:
Sacrificial fill materials serve as intermediary substances that occupy the source or drain region spaces during gate cut formation. These materials protect the actual source or drain regions from etching damage while allowing the gate cut structures to be formed, and are later removed to reveal the intact source or drain regions.
2Productivity
If gate cut structures are formed early in the process, then fabrication steps are reduced, but etching interference with source or drain regions occurs
Solution Approach 1:
Sacrificial fill materials act as intermediary protective elements during the gate cut formation process. They absorb the etching action that would otherwise harm the source or drain regions, allowing early gate cut formation to proceed without causing etching interference to the active device regions.
Solution Approach 2:
Sacrificial fill materials are temporary, disposable structures used only during the gate cut formation process. They are intentionally designed to be removed after serving their protective function, enabling the process to proceed efficiently without permanent additional structures.
3Reliability
If source or drain regions are formed before gate cut structures, then region integrity is maintained, but additional fabrication steps are required
Solution Approach 1:
The formation of source or drain regions using sacrificial fill materials is merged with the subsequent gate cut formation process. Instead of treating them as separate operations, the sacrificial fill serves dual purposes: defining the source or drain regions and protecting them during gate cut formation, thereby reducing overall process complexity.
Solution Approach 2:
The sacrificial fill materials perform multiple functions: they define the source or drain region boundaries, protect these regions during gate cut formation, and serve as placeholders that are later removed. This multi-functionality reduces the need for separate protective measures and simplifies the overall fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains the integrity of source and drain regions by avoiding interference during gate cut formation, ensuring precise and reliable transistor structure integrity.
Implementation Method 1
a dielectric liner on at least a sidewall and/or top surface of the first source or drain region and also on at least a portion of a sidewall of the gate cut structure adjacent to the first source or drain region
Implementation Method 2
subsequent epitaxial growth of source or drain regions
Data Source
AI summary
Techniques are provided herein to form semiconductor devices having gate cut structures. Adjacent semiconductor devices having semiconductor regions (e.g., fins or nanoribbons) extending in a first direction have a gate structure that extends over the semiconductor regions in a second direction and are separated by a gate cut structure extending in the first direction and interrupting the gate structure. The gate cut structure further extends between adjacent source or drain regions (corresponding to the adjacent semiconductor devices). A dielectric liner on at least a sidewall and/or top surface of the source or drain regions and also extends up a sidewall surface of the gate cut structure. In some cases, the gate structure includes a gate dielectric present on the semiconductor regions, but not present on the gate cut structure. A contact may pass through the liner and at least partially land on a source or drain region.