Backside Gate Cut Fill Structure for Etch Damage and Vt Tuning
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Solution Overview
Problem
Conventional methods for fabricating field-effect transistors, such as FinFETs and nanosheet devices, face challenges in scaling down device sizes due to device performance degradation and increased fabrication costs, particularly in maintaining effective gate control and mitigating short-channel effects.
Innovation Solution
The method involves forming a gate cut feature from the backside of a substrate, depositing a sacrificial material within the trench formed by removing a portion of the gate structure, filling the trench with a dielectric material, and partially removing the sacrificial material to insert a work-function metal layer, which repairs any damage and enhances device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is scaled down to increase functional density, then production efficiency and cost are improved, but device performance degrades due to loss of gate control and short-channel effects
Solution Approach 1:
The patent introduces a backside gate structure that applies control from the vertical dimension (substrate side) in addition to the conventional top gate control. This multi-dimensional gating approach maintains effective channel control even as device dimensions are scaled down, preventing short-channel effects while allowing continued miniaturization for higher productivity
Solution Approach 2:
The gate control is segmented into two independent components: a top gate for primary channel control and a backside gate formed by modifying the substrate. This segmentation allows each gate to be optimized independently and provides redundant control mechanisms that maintain device performance at scaled dimensions
2Ease of manufacture
If conventional gate cut features are used to isolate gate structures, then fabrication is simplified, but damage from etching processes increases and device performance deteriorates
Solution Approach 1:
The patent introduces a sacrificial material as an intermediary substance that protects the gate structure during etching processes. This sacrificial layer is temporarily deposited, patterned, and etched away to create the gate cut feature, thereby mediating between the etching tool and the gate structure to prevent direct damage while maintaining fabrication simplicity
Solution Approach 2:
The sacrificial material is deposited and patterned before the actual gate cut etching process. This preliminary action prepares a protective template that guides the subsequent etching, ensuring that the gate structure is not directly exposed to harsh etching conditions and reducing damage while maintaining ease of manufacture
3Ease of manufacture
If standard dielectric filling is used for gate cut features, then manufacturing is straightforward, but threshold voltage tuning capability is lost
Solution Approach 1:
The patent applies different material properties to different regions of the gate cut feature. The sacrificial material is selectively deposited and removed in specific patterns, and the subsequent filling material is chosen based on local requirements for threshold voltage tuning. This local differentiation maintains ease of manufacture through standard processes while enabling versatile threshold voltage control
Data Source
AI summary
A semiconductor structure includes a gate structure surrounding a plurality of channels and a cut feature that electrically isolates two separate portions of the gate structure. The cut feature comprises an outer layer having a work-function metal, and an inner layer comprising a dielectric material. The cut feature extends above a top surface of the gate structure.