Self-Aligned Gate Cut Isolation for FinFET Arrays
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Solution Overview
Problem
Current methods for isolating adjacent gate electrodes on fin-based semiconductor devices face challenges due to overlay-related inaccuracies as dimensions decrease, requiring complex processes and planarization steps that are incompatible with standard fin heights.
Innovation Solution
A method involving dual stack semiconductor fins with a monocrystalline base and polycrystalline portions, where shallow trench isolation is filled with oxide and polycrystalline material, followed by thermal oxidation to form oxide strips for self-aligned etching, allowing for the creation of gate cut structures without lithographic patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If classic lithographic techniques are used for gate cut isolation, then the process is simple, but overlay-related inaccuracies occur as dimensions decrease
Solution Approach 1:
The gate cut isolation structure is self-aligned to the fin structure through the spacer formation process. The spacer automatically positions itself at a precise distance from the fin, eliminating the need for separate lithographic alignment steps. This self-service mechanism ensures high manufacturing precision without complex lithographic overlay procedures.
Solution Approach 2:
A spacer structure is introduced as an intermediary element between the fin and the isolation structure. This spacer serves as a positioning mediator that defines the exact location of the gate cut isolation, transferring the alignment function from lithography to the spacer formation process, thereby improving overlay accuracy.
2Manufacturing precision
If dummy spacers are produced on both sides of fins to create gate cut structures, then isolation precision improves, but process complexity increases
Solution Approach 1:
The fin structure is selectively removed from specific locations in the array to create the gate cut isolation. By taking out the fin material at designated positions and replacing it with isolation material, the method achieves precise isolation structure dimensions without requiring complex dummy spacer formation and thickness control procedures.
Solution Approach 2:
Instead of adding dummy spacers to define the isolation location, the method inverts the approach by directly removing the fin material at the isolation location and filling with isolation material. This inversion simplifies the process by eliminating the dummy spacer formation, deposition, and thickness control steps while maintaining isolation precision.
3Manufacturing precision
If planarization steps are performed for gate cut isolation, then isolation structure formation is enabled, but fin height is reduced
Solution Approach 1:
The gate cut isolation structure is formed at an early stage in the fabrication process, before any planarization steps are performed. By completing the isolation structure formation preliminarily, the fin height is preserved and not reduced by subsequent planarization operations. The isolation structure is created by direct fin removal and filling, enabling isolation formation without fin height reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and efficient isolation of gate electrodes without reducing fin height, simplifying the process and improving accuracy, making it suitable for dense arrays of fin structures.
Implementation Method 1
a thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each of the openings, thereby obtaining two oxide strips adjacent the exposed fin
Data Source
AI summary
A substrate includes on its surface an array of dual stack semiconductor fins, each fin comprising a monocrystalline first portion, a polycrystalline second portion, and a mask third portion. Trenches between the fins are filled with shallow trench isolation (STI) oxide and with polycrystalline material, after which the surface is planarized. Then a second mask is produced on the planarized surface, the second mask defining at least one opening, each defined opening extending across an exposed fin. A thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each defined opening, thereby producing two oxide strips in each defined opening. Using the second mask and the oxide strips as a mask for self-aligned etching, the material of the exposed dual stack fins is removed and subsequently replaced by an electrically isolating material, thereby creating gate cut structures.