Gate Cut Isolation via Dummy Gate Sidewall Deposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In advanced IC fabrication, particularly at the 7 nm technology node, forming gate cut openings with precise dimensions is challenging due to the narrowing of spacing between structures, leading to issues with residue removal and bowed sidewalls during reactive ion etch processes, which can cause shorts and hinder the formation of a work function metal layer.
Innovation Solution
A method involving the formation of a dummy gate material mandrel with a sidewall, a gate cut dielectric layer, and subsequent deposition of a dummy gate material to create a gate cut isolation with a non-vertical longitudinal axis, eliminating the need for defining a gate cut critical dimension and allowing for precise electrical isolation between gate conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional reactive ion etch (RIE) is used to form gate cut openings at 7 nm node, then the etching process can be performed, but the amorphous silicon and liner spacer pinch off in the narrow gate cut, making residue removal extremely difficult
Solution Approach 1:
The gate cut isolation layer is formed preliminarily before the gate conductor deposition. This preliminary formation allows the isolation structure to be in place before the gate material is deposited, enabling better control over the final gate cut geometry and facilitating easier residue removal without compromising the narrow dimensions required for 7 nm node devices.
Solution Approach 2:
Instead of forming the gate cut opening first and then adding isolation material, the patent inverts the sequence by first forming the gate cut isolation layer and then creating the opening through it. This reversal allows the isolation structure to guide the etching process and prevents the pinch-off problem that occurs when trying to etch narrow openings through pinch-off-prone materials.
2Ease of manufacture
If high bias power RIE overetch is applied to remove residue, then residue can be removed, but bowed sidewalls are created in the gate cut opening, which can create shorts with the gate conductor ends
Solution Approach 1:
The gate cut isolation layer is formed in advance before the gate conductor deposition. This preliminary structure serves as a protective framework that prevents the formation of bowed sidewalls during subsequent etching processes, thereby eliminating the risk of shorts between gate conductor ends while still allowing effective residue removal.
Solution Approach 2:
The gate cut isolation layer acts as a cushioning structure formed beforehand to protect against the harmful effect of bowed sidewalls. This preliminary protective layer prevents the etching process from creating the problematic bowed geometry that would lead to shorts, thus cushioning against potential reliability failures.
3Ease of manufacture
If conventional gate cut fill size of 30 nm is used, then sufficient space is provided to remove residue, but the spacing becomes too large for 7 nm technology node finFETs, preventing sufficient metal gate conductor separation
Solution Approach 1:
The gate cut isolation layer is formed preliminarily with precise dimensions suitable for 7 nm node, before any gate conductor material is deposited. This preliminary formation establishes the correct narrow spacing (less than 30 nm) that enables sufficient metal gate conductor separation while still allowing residue removal through the pre-formed isolation structure rather than requiring large opening spaces.
Solution Approach 2:
The patent changes the critical parameter of gate cut opening width from the conventional 30 nm to a smaller dimension appropriate for 7 nm node devices. By forming the gate cut isolation layer first, this parameter change is achieved without compromising the ability to remove residue, as the isolation structure provides the necessary pathways for residue clearance even at reduced dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of a very thin, non-vertical gate cut isolation, ensuring effective electrical isolation between gate conductors while avoiding the challenges of small opening fillings and residue removal, thus supporting the fabrication of integrated circuits at smaller technology nodes.
Implementation Method 1
forming a gate cut dielectric layer against the sidewall of the dummy gate material mandrel
Implementation Method 2
forming a gate cut dielectric layer against the sidewall of the dummy gate material mandrel
Implementation Method 3
conventional reactive ion etch (RIE)
Data Source
AI summary
A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.