Gate Cut Isolation Formation with Mask Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
At the 7 nanometer technology node and beyond, forming gate cut openings with precise size and removing residue from these openings is challenging due to amorphous silicon or polysilicon pinch-off and nitride liner residue, which can block subsequent etching processes and cause transistor shorts.
Innovation Solution
A method involving forming a gate cut opening in a gate material layer with a nitride liner and an oxide body inside, using a contact forming process mask to protect the gate cut isolation, allowing for effective electrical isolation between metal gate conductors and preventing nitride residue creation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional RIE is used to form gate cut openings at 7nm node, then etching process is simple, but amorphous silicon or polysilicon pinch-off occurs making residue removal difficult
Solution Approach 1:
The patent changes the etching parameters by switching from conventional RIE to a two-step etch process with different chemistries (CHF3 followed by CF4). This parameter change allows precise gate cut opening formation while preventing amorphous silicon or polysilicon pinch-off, enabling complete residue removal.
Solution Approach 2:
The etching process is segmented into two distinct steps: first etching with CHF3 to create the gate cut opening, then etching with CF4 to remove residue. This segmentation of the etching process solves the contradiction by allowing each step to be optimized for its specific function.
2Reliability
If nitride is used for gate cut isolation, then electrical isolation is achieved, but nitride residue is created during etching that blocks subsequent processes
Solution Approach 1:
The patent converts the harmful nitride residue into a beneficial protective layer. The nitride liner that would normally cause blocking is instead used as an etch stop layer during contact hole formation, protecting the gate cut isolation while enabling subsequent processing.
Solution Approach 2:
The nitride liner acts as an intermediary between the gate cut isolation and the contact hole etching process. It serves as both the isolation material and the etch stop layer, mediating between electrical isolation requirements and subsequent processing needs.
3Area of moving object
If gate cut opening size is reduced to accommodate smaller spacings, then transistor density increases, but residue removal becomes more difficult
Solution Approach 1:
The patent changes the etching chemistry parameters to enable residue removal from smaller gate cut openings. The two-step etch process with CHF3 and CF4 provides the necessary precision for complete residue removal even when opening sizes are reduced for higher transistor density.
Data Source
AI summary
A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.