Gate Cut Last Metal Gate Trench Etching for Shorting Prevention
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Solution Overview
Problem
Metal residue along the edges of gate stacks in MOSFETs causes shorting issues, particularly as devices are scaled down to the 7 nanometer footprint, leading to epitaxial shorting and unwanted issues in semiconductor formation.
Innovation Solution
The CT cut last process is employed, where a trench is etched and formed last, following the formation of gate stacks, to remove work function metal residues and prevent epitaxial shorting, along with the deposition of a conformal low-k dielectric layer to fill and pinch off trenches, thereby eliminating metal residue and reducing shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If device size is scaled down to 7 nanometer footprint, then integration density is improved, but metal residue causes shorting issues
Solution Approach 1:
The patent performs the trench etching operation after gate stack formation rather than before, allowing the etch process to automatically remove work function metal residues from gate edges. This preliminary cleaning action prevents epitaxial shorting before it can occur during subsequent processing steps.
Solution Approach 2:
The patent extracts and removes work function metal residues from gate stack edges through the trench etching process. By etching trenches that extend through the gate stack, the harmful metal residues are completely removed, eliminating the source of potential shorting paths.
2Ease of manufacture
If trench is etched before gate stack formation, then contact alignment is simplified, but work function metal residues remain causing shorting
Solution Approach 1:
The patent inverts the conventional process sequence by etching trenches after gate stack formation instead of before. This reversal allows the etch process to serve dual purposes: defining contact regions and simultaneously removing work function metal residues from gate edges, eliminating shorting without complicating alignment.
Solution Approach 2:
The patent converts the previously harmful work function metal residues into a beneficial cleaning opportunity. By timing the trench etch to occur after gate formation, the etch process naturally removes residues that would otherwise cause shorting, turning a potential defect into a self-cleaning mechanism.
3Device complexity
If conventional etching process is used, then trench formation is simple, but metal residue causes epitaxial shorting
Solution Approach 1:
The patent performs the trench etching operation after gate stack formation to enable automatic removal of work function metal residues. This timing ensures that any metal residues are cleaned before epitaxial growth occurs, preventing shorting without requiring additional cleaning steps.
Solution Approach 2:
The etching process serves itself by simultaneously performing two functions: defining the contact trench geometry and cleaning work function metal residues from gate edges. This self-cleaning capability eliminates the need for separate residue removal steps while maintaining process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maximizes scaling potential, reduces epitaxial shorting, and provides additional tolerance for alignment and separation in SRAM, effectively eliminating shorting between gate stacks and contacts.
Implementation Method 1
depositing a conformal low-k dielectric layer over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region
Data Source
AI summary
A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.