Gate Cut Offset Layout for GAA Nanowire Via Landing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit fabrication lies in optimizing device performance and via landing due to constraints on lithographic processes as feature dimensions shrink, particularly with multi-gate transistors like tri-gate transistors, where the gate cut placement limits routing options and via landing, leading to potential yield concerns.
Innovation Solution
Implementing a gate cut offset from the cell center in gate-all-around devices, allowing for reduced ribbon width and increased via landing margin, and using a 'plug-last' approach for metal gate cut processes to enhance metal fill capability and reduce space constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate cut is placed at the cell center in conventional processes, then routing options are limited and via landing is constrained, but this placement is simpler to manufacture
Solution Approach 1:
The patent applies asymmetry by offsetting the gate cut from the cell center to a non-central position. This asymmetric placement creates additional space on one side of the gate structure, enabling improved via landing margins and more flexible routing configurations for metal interconnects, thereby resolving the contradiction between manufacturing simplicity and routing adaptability.
2Productivity
If feature dimensions are shrunk to increase device density, then capacity increases, but lithographic process constraints become overwhelming
Solution Approach 1:
The patent addresses lithographic constraints by optimizing the two-dimensional layout arrangement of gate cuts and via holes. By strategically positioning the gate cut offset and adjusting the pitch between features in the planar dimension, the design achieves higher device density while maintaining manufacturability within existing lithographic process capabilities, effectively navigating the trade-off between density and precision.
3Reliability
If ribbon width is reduced to increase via landing margin, then via landing improves, but space constraints increase
Solution Approach 1:
The offset gate cut creates an asymmetric space distribution that provides enhanced via landing margin on the offset side while maintaining adequate spacing on the other side. This asymmetric layout allows the ribbon width to be optimized for via landing without uniformly increasing space constraints across the entire cell, thereby improving reliability while managing area efficiency.
Data Source
AI summary
Integrated circuit structures having gate cut offset, and methods of fabricating integrated circuit structures having gate cut offset, are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion, the gate cut laterally closer to the second vertical stack of horizontal nanowires than to the first vertical stack of horizontal nanowires.