Gate Cut Plug Structure With Hermetic Liner for Low Gate Capacitance
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Solution Overview
Problem
As integrated circuit (IC) devices miniaturize, high capacitance between adjacent transistor gates due to high-permittivity dielectric materials and oxygen-containing low-K materials cause performance issues and unpredictable threshold voltage shifts.
Innovation Solution
Implementing low-permittivity dielectric materials with minimal oxygen content, such as silicon dioxide, and a thin hermetic liner layer to isolate transistor gates, reducing parasitic capacitance and protecting gate metals from oxidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-permittivity dielectric materials (e.g., silicon nitride) are used to separate adjacent transistor gates, then gate separation is achieved, but capacitance between adjacent gates increases, impairing device performance
Solution Approach 1:
The patent changes the dielectric constant parameter by selecting low-K materials (silicon oxide with K≈3.9) instead of high-K materials (silicon nitride with K≈7.5), directly reducing the capacitance between adjacent gates and improving device performance
Solution Approach 2:
The patent employs a composite structure combining low-K dielectric material (silicon oxide) with a hermetic liner layer, creating a multi-material system that simultaneously achieves low capacitance and oxidation protection
2Reliability
If low-permittivity materials (e.g., silicon oxide) are used to reduce capacitance, then device performance improves, but oxygen content in the material increases, causing gate metal oxidation and threshold voltage shifts
Solution Approach 1:
The hermetic liner layer acts as an intermediary barrier between the low-K dielectric material and the gate metal, preventing oxygen diffusion from the dielectric to the metal while allowing the low-K material to maintain its capacitance-reducing function
Solution Approach 2:
The patent creates a composite structure where the hermetic liner (nitrogen-containing material) and low-K dielectric (oxygen-containing material) work together, with the liner protecting the gate metal from oxidation while the dielectric reduces capacitance
3Reliability
If a hermetic liner layer is added to protect gate metals from oxidation, then threshold voltage stability improves, but device complexity and manufacturing steps increase
Solution Approach 1:
The hermetic liner is implemented as a thin film layer deposited conformally on the gate structure, providing oxidation protection without adding significant structural complexity or volume to the device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances IC device performance by minimizing capacitance and stabilizing threshold voltages, thereby improving operating speeds and reducing process variation.
Implementation Method 1
a thin hermetic liner layer to isolate transistor gates, reducing parasitic capacitance and protecting gate metals from oxidation
Implementation Method 2
low permittivity (or 'low-K') materials might otherwise be desired, low-K materials (such as silicon oxide) often contain higher proportions of oxygen, and deposition of oxygen-containing materials on gate metal results in metal oxidation
Data Source
AI summary
Integrated circuit (IC) device isolation structures between transistor gates. An IC device may include an electrically insulating structure between metal gates of adjacent transistors, and the insulating structure may include a dielectric liner around a different dielectric fill material and on sidewalls of the adjacent metal gates. The dielectric liner may be much thinner than the dielectric fill material. A metal via may be through, and in contact with, the dielectric fill material. The adjacent transistors and metal gates may be between frontside and backside interconnect structures, and the metal via may extend between, and couple, the interconnect structures.