Gate Cut PMOS Transistor Cell Layout for Ultra-Low Threshold Voltage
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Solution Overview
Problem
Current approaches to achieving ultra-low PMOS threshold voltage in integrated circuits face challenges such as work function metal tuning difficulties, dopant implantation causing mobility degradation, and dipole formation complications, which hinder the development of efficient computational devices for complex system modeling.
Innovation Solution
The implementation of a gate cut layout in transistor cells, where PMOS transistors without gate cuts experience increased strain, resulting in a lower threshold voltage, while NMOS transistors maintain suitable mobility, allowing for the design of ultra-low voltage transistor cells with improved circuit flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If work function metal tuning is used to achieve ultra-low PMOS threshold voltage, then PMOS threshold voltage is reduced, but filling narrow gate trenches becomes difficult
Solution Approach 1:
The patent changes the work function parameter of the gate electrode by selecting specific metal materials (such as tungsten, titanium nitride, tantalum nitride) with appropriate work functions to achieve ultra-low PMOS threshold voltage without modifying the gate trench structure or filling process
Solution Approach 2:
The patent uses standard semiconductor manufacturing materials and processes that are already widely available and cost-effective, avoiding the need for specialized or expensive materials that would be required to solve the narrow trench filling problem
2Manufacturing precision
If dopant implant is used to achieve ultra-low PMOS threshold voltage, then PMOS threshold voltage is reduced, but mobility degrades
Solution Approach 1:
The patent replaces the mechanical/dopant-based threshold voltage control method with an electrical field-based method using work function engineered gate electrodes, thereby achieving threshold voltage control without introducing dopant-induced mobility degradation
Solution Approach 2:
The patent changes the electrical parameter (work function) of the gate electrode to control PMOS threshold voltage, providing an alternative to dopant concentration control that preserves carrier mobility while achieving the desired threshold voltage
3Manufacturing precision
If dipole formation is used to achieve ultra-low PMOS threshold voltage, then PMOS threshold voltage is reduced, but processing becomes complicated
Solution Approach 1:
The patent extracts and eliminates the complex dipole formation processing steps by using work function metal tuning alone to achieve ultra-low PMOS threshold voltage, thereby simplifying the overall device fabrication process
Solution Approach 2:
The patent achieves the desired electrical characteristic (ultra-low threshold voltage) by changing the material parameter (work function) of the gate electrode rather than introducing additional processing steps for dipole formation
4Reliability
If gate cut layout is avoided to increase PMOS mobility through strain, then PMOS threshold voltage decreases, but NMOS threshold voltage control becomes difficult
Solution Approach 1:
The patent applies different work function metals or metal combinations to PMOS and NMOS gate electrodes, creating local quality differences that allow independent optimization of PMOS threshold voltage and NMOS threshold voltage even in a shared gate structure without gate cuts
Solution Approach 2:
The patent segments the gate electrode into functionally distinct regions with different work function materials, allowing independent control of PMOS and NMOS threshold voltages while maintaining the benefits of a shared gate structure for mobility enhancement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively achieves ultra-low PMOS threshold voltage with enhanced PMOS mobility and NMOS threshold voltage control, providing increased circuit design flexibility and computational efficiency.
Implementation Method 1
PMOS transistors without gate cuts experience increased strain, resulting in a lower threshold voltage
Data Source
AI summary
Integrated circuit dies, apparatuses, systems, and techniques, are described herein related to low and ultra-low threshold voltage transistor cells. A first transistor cell includes separate semiconductor bodies contacted by separate gate electrodes having a dielectric material therebetween. A second transistor cell includes separate semiconductor bodies contacted by a shared gate electrode that couples to both semiconductor bodies. Transistors of the second transistor cell may be operated at a lower threshold voltage than those of the first transistor cell due to increased strain on the semiconductor bodies from the shared gate electrode.