Self-aligned Gate Cut via Polysilicon Liner Oxidation
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Solution Overview
Problem
The etch process for forming gate structures in semiconductor devices, such as FinFETs, is prone to misalignment due to lithography limitations and increased device scaling, making it difficult to achieve precise gate-cutting between adjacent semiconductor devices.
Innovation Solution
A method and structure that employ a selective etch process sequence combined with a masking sequence using a nitride containing layer, a polysilicon containing layer, and a nitride pinch off fill between close pitch fin structures, along with an oxidation treatment, to enable self-aligned gate cutting, ensuring accurate alignment and separation of gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography and etch processes are used for gate structure formation, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to misalignment between adjacent semiconductor devices
Solution Approach 1:
The patent applies preliminary action by forming a polysilicon liner layer and performing selective oxidation before the final gate-cut etch process. The polysilicon liner is deposited and oxidized in advance to create a protective oxide layer that will serve as an etch mask during subsequent processing, ensuring precise alignment is achieved before the actual gate cutting occurs.
Solution Approach 2:
The patent uses an intermediary approach by introducing a polysilicon containing layer as a mediator between the gate structure and the etch process. This intermediate layer is selectively oxidized to form an oxide material layer that acts as a protective mask during gate-cut etching, enabling precise alignment without requiring complex lithography adjustments.
2Productivity
If device scaling is reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates due to increased difficulty in achieving precise gate-cutting
Solution Approach 1:
The patent applies self-service by using the polysilicon liner layer's own oxidation properties to create a self-aligned etch mask. The selective oxidation of the polysilicon liner automatically generates the protective oxide layer at the precise location needed for gate-cutting, eliminating the need for separate alignment procedures and ensuring accuracy even at reduced device scales.
Solution Approach 2:
The patent changes material parameters by converting the polysilicon containing layer into an oxide material layer through selective oxidation. This parameter change transforms the polysilicon layer into a material with different etch resistance properties, creating a natural mask that enables precise gate-cutting at scaled dimensions without compromising alignment precision.
3Manufacturing precision
If selective etch process sequence with polysilicon liner oxidation is used, then manufacturing precision is improved for gate-cutting alignment, but device complexity increases due to additional process steps
Solution Approach 1:
The patent applies universality by making the polysilicon containing layer perform multiple functions: it serves as a structural layer in the material stack, acts as a precursor for the selective oxidation mask, and provides alignment reference for the gate-cut etch process. This multi-functionality reduces the need for separate dedicated mask layers, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent applies discarding and recovering by temporarily using the polysilicon containing layer as a mask precursor that is selectively oxidized and then removed after serving its protective function during gate-cut etching. The polysilicon layer is discarded after conversion to oxide and subsequent removal, having fulfilled its purpose of enabling precise alignment without permanently increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise self-aligned gate cutting, reducing misalignment issues and improving the accuracy of gate structure formation, even at smaller device scales, thereby enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
The semiconductor containing layer is converted into an oxide material layer
Data Source
AI summary
A method of forming a semiconductor device that includes forming a gate structure over a plurality of fin structures, wherein the gate structure provides a first fill pinch off between the fin structures separated by a first pitch; and forming a material stack of a silicon containing layer, and a dielectric layer over the plurality of fin structures, wherein the dielectric provides a second fill pinch off between fin structures separated by a second pitch. The silicon containing layer is converted into an oxide material layer. The second dielectric that provides the second fill pinch off is removed, and an opening is etched in a remaining silicon containing layer exposed by removing the second fill pinch off. An underlying gate cut region is etched in the gate structure using the opening in the remaining portion of the silicon containing layer.