Gate Cut PUF for Unique Chip Identification
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Solution Overview
Problem
Current security measures for electronic devices, particularly integrated circuits, lack a reliable method to uniquely identify each device without additional process costs, making it challenging to distinguish between them effectively.
Innovation Solution
A semiconductor chip with a physical unclonable function (PUF) region is created by implementing a gate cut (CT) design that results in random complete or incomplete gate cuts based on natural process variations, using fin field-effect transistors (FinFETs) to generate a unique security code without additional process costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional security measures are used for electronic devices, then device security is provided, but reliable unique identification of each device is not achieved
Solution Approach 1:
The semiconductor device automatically generates a unique identification code through inherent manufacturing process variations. The gate cut design exploits natural variations in etch depth and gate material deposition to create distinct electrical characteristics for each device, eliminating the need for external identification mechanisms while providing reliable unique identification
Solution Approach 2:
The invention changes the electrical parameters of the semiconductor device by introducing a gate cut design that creates varying resistance values. The gate material (such as tungsten) is deposited to a thickness that results in incomplete coverage, creating a resistance value that serves as a unique identifier. This parameter change transforms the device's electrical characteristics into an identification mechanism
2Measurement precision
If additional process steps are added to generate unique device identifiers, then device distinguishability is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The gate structure serves dual purposes: it functions as the control electrode for the transistor operation and simultaneously acts as the source of unique identification. The gate cut design that creates resistance variation is integrated into the standard manufacturing process, allowing the same structural feature to provide both electrical functionality and identification capability without adding separate processes
Solution Approach 2:
The gate material deposition process acts as an intermediary that naturally creates variation. By controlling the deposition thickness to be insufficient for complete coverage, the process inherently generates unique resistance values for each device. This intermediary approach leverages the deposition process itself to create identification features rather than requiring additional steps
Data Source
AI summary
Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip includes a substrate. The semiconductor chip includes multiple devices formed on the substrate. Each device includes multiple fins. A gate is formed on the multiple fins with a gate cut (CT) design that results in random distribution of complete gate cut and incomplete gate cut for each of the multiple devices based on a natural process variation in semiconductor manufacturing for each device. A physical unclonable function (PUF) region is defined in accordance with the random distribution.