Gate Cut Spacer Removal for FET Reliability
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Solution Overview
Problem
As the critical dimension of sacrificial gate structures shrinks, the difficulty in completely removing them increases, leading to potential electrical shorts between functional gate structures due to incomplete removal, which affects the reliability of field-effect transistors.
Innovation Solution
A method involving the formation of spacers adjacent to gate structures, partial etching to create cuts, and selective removal of spacer sections to facilitate complete removal of sacrificial gate structures, followed by deposition of dielectric pillars to ensure electrical isolation between gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the critical dimension of sacrificial gate structures is reduced to achieve higher device density, then device integration is improved, but the difficulty of completely removing the sacrificial gate structure increases
Solution Approach 1:
The method performs preliminary actions by forming spacers adjacent to the sacrificial gate structure before etching, and selectively removing portions of the sacrificial gate structure in a controlled sequence. This preliminary preparation enables complete removal by creating access pathways and preventing premature bridging, thereby resolving the contradiction between reduced dimensions and removal difficulty
Solution Approach 2:
The sacrificial gate structure removal process is segmented into multiple controlled etching steps with intermediate spacer removal. This segmentation allows the etching process to proceed through the narrowed critical dimension in manageable stages, preventing complete bridging while ensuring thorough removal, thus enabling complete removal despite reduced critical dimensions
2Productivity
If the sacrificial gate structure is not completely removed, then manufacturing time is reduced, but electrical shorts between functional gate structures occur
Solution Approach 1:
The method performs preliminary spacer formation and selective sacrificial gate removal before final dielectric deposition. This preliminary action ensures complete removal and electrical isolation are achieved before subsequent processing steps, preventing shorts while maintaining manufacturing efficiency by integrating removal into the existing process flow
Solution Approach 2:
Spacers serve as intermediary structures that facilitate the complete removal process. They are formed adjacent to the sacrificial gate structure, selectively removed to enable thorough etching access, and ultimately discarded after serving their mediating function. This intermediary approach ensures complete removal without requiring excessive manufacturing time
3Manufacturing precision
If aggressive etching is used to ensure complete removal, then removal completeness is improved, but damage to surrounding structures increases
Solution Approach 1:
The etching process is applied with local quality control through the use of spacers that define precise etching boundaries. The spacers protect adjacent regions from aggressive etching while allowing thorough removal of the sacrificial gate structure in targeted areas. This localized approach ensures complete removal without damaging surrounding functional structures
Solution Approach 2:
Spacers act as intermediary protective structures during the etching process. They are positioned adjacent to the sacrificial gate structure and selectively removed to control etching penetration depth and lateral spread. This intermediary protection enables aggressive etching where needed while preventing damage to surrounding structures, resolving the contradiction between removal completeness and structural integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures complete removal of sacrificial gate structures, reducing the likelihood of electrical shorts and mitigating issues like polymer pinch-off and silicon residue accumulation, thereby enhancing the reliability of field-effect transistors.
Implementation Method 1
patterning a section of the gate structure with a first etching process to form a cut that extends partially through the gate structure
Implementation Method 2
A dielectric material is deposited inside the cut to form a dielectric pillar
Data Source
AI summary
Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.