Gate Cut Stressor Layout for Transistor Mobility Enhancement

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Solution Overview

Problem

Existing semiconductor device fabrication methods do not effectively utilize stress materials within the gate cut region to enhance transistor performance, particularly in fin field effect transistors (FETs) and nanosheet transistors, limiting mobility improvements.

Innovation Solution

Incorporating a gate cut stressor with intrinsic tensile force within the gate cut region, applied perpendicular to the fins, to create tensile stress in the gates and compressive stress in the fins, improving hole and electron mobility through the Poisson effect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If no stress material is used in the gate cut region, then the device structure is simple and manufacturing is easier, but mobility improvement is limited

Engineering Contradiction:
Improvestructural simplicityVSAvoidmobility improvement
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent applies stress material specifically in the gate cut region rather than uniformly across the entire device. This localized application provides mobility improvement where needed (in the channel region under the gate cut) while maintaining structural simplicity elsewhere, resolving the contradiction between ease of manufacture and mobility enhancement.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the physical parameter of stress application by introducing stress material with specific intrinsic stress properties into the gate cut region. This parameter change (from no stress to controlled stress) directly improves carrier mobility without fundamentally altering the overall device structure or manufacturing process complexity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If stress material is added to the gate cut region, then mobility improvement is enhanced, but device complexity increases

Engineering Contradiction:
Improvemobility improvementVSAvoidstructural complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

By confining the stress material to the gate cut region only, the patent achieves mobility improvement in the critical channel area without adding complexity to other device regions. The stress material is placed precisely where it is needed to enhance carrier mobility, while the rest of the device maintains its original simple structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The stress material acts as an intermediary element that mediates between the gate structure and the channel, providing the necessary stress to improve mobility without directly modifying the gate or channel structures themselves. This intermediary approach enhances performance while adding minimal structural complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances mobility in both holes and electrons within the transistors, particularly beneficial for CMOS switching devices, by applying tensile stress to the gates and compressive stress to the fins, thereby improving device performance.

Implementation Method 1

improving hole and electron mobility through the Poisson effect

Methodology Applied
Scientific EffectPoisson effect: Poisson's Effect

Data Source

PatentUS12402391B2Stressed material within gate cut region
Publication Date: 2025.08.26 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12402391B2 patent drawing
  • US12402391B2 patent drawing
  • US12402391B2 patent drawing

AI summary

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.