Self-Aligned Gate Cut Layout for Precise Trench Isolation
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Solution Overview
Problem
As integrated circuits scale downward in size, forming self-aligned gate cuts between densely packed transistors becomes challenging due to issues like uneven heights, alignment errors, and detrimental impacts on conductive features, leading to poor yield and performance variation.
Innovation Solution
The formation of self-aligned gate cuts is achieved by depositing a sacrificial material over adjacent semiconductor devices within the gate trench after forming the gate dielectric, etching a recess, and filling it with dielectric material, which is then converted into a gate cut confined within the trench, followed by a dielectric plug to ensure complete separation of gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate cut formation methods are used, then gate cuts can be formed between transistors, but alignment errors occur and gate cuts extend beyond the gate trench causing poor yield
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial material structure within the gate trench before forming the gate cut. This sacrificial structure pre-defines the precise location and boundaries of the gate cut, ensuring it remains confined within the trench. The gate cut is then formed by removing this pre-positioned sacrificial material, which eliminates alignment errors and prevents the gate cut from extending beyond the trench boundaries.
Solution Approach 2:
The patent uses a sacrificial material as an intermediary element to achieve precise gate cut formation. This sacrificial material temporarily occupies the space where the gate cut will eventually be formed, serving as a mediator that defines the exact boundaries. After the gate cut is formed by removing the sacrificial material, the intermediary has fulfilled its purpose of ensuring precise alignment and confinement within the gate trench.
2Area of moving object
If transistors are packed more densely to reduce device size, then device spacing is reduced, but forming isolation structures becomes challenging
Solution Approach 1:
The patent applies segmentation by dividing the gate structure into separate segments through precise gate cuts between adjacent transistors. This segmentation allows each transistor's gate to be independently formed and isolated, making it easier to manufacture isolation structures even when transistors are densely packed. The gate cuts create clear boundaries that simplify the formation of isolation structures in high-density configurations.
Solution Approach 2:
The sacrificial material is deposited and patterned beforehand to pre-establish the gate cut locations and boundaries. This preliminary action creates a template that guides subsequent processing steps, making it easier to form isolation structures between densely packed transistors. The pre-defined boundaries from the sacrificial material eliminate the need for complex alignment procedures during isolation structure formation.
3Ease of manufacture
If gate cuts are formed before gate metallization, then gate cuts can be made, but uneven heights and alignment errors occur
Solution Approach 1:
The sacrificial material serves as an intermediary that is deposited conformally over the gate dielectric and transistor structures. This intermediary layer is then selectively removed to form the gate cut, ensuring that the cut is perfectly aligned with the underlying structures. The sacrificial material acts as a template that maintains precise alignment throughout the process, eliminating the uneven heights and alignment errors that occur with conventional methods.
Solution Approach 2:
The sacrificial material is deposited and patterned in advance to pre-establish the exact gate cut boundaries. This preliminary positioning ensures that when the gate cut is formed by removing the sacrificial material, it will be perfectly aligned with the gate trench and surrounding structures. The pre-defined boundaries eliminate alignment errors and ensure uniform heights across the structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method results in precisely aligned gate cuts that do not extend beyond the gate trench, improving yield and consistency by isolating gate structures effectively without affecting other conductive features.
Implementation Method 1
depositing a sacrificial material over adjacent semiconductor devices within the gate trench
Implementation Method 2
etching a recess, and filling it with dielectric material
Data Source
AI summary
Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through at least a portion of the entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. A dielectric plug contacts a top surface of the gate cut to separate the gate structure on either side of the dielectric plug. The gate cut is self-aligned between the adjacent semiconductor devices such that it is substantially equidistant between the semiconductor devices along the gate trench.