Gate Cut-Fill Profile for FinFET Source/Drain Protection
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Solution Overview
Problem
As the semiconductor industry advances to nanometer technology process nodes, challenges arise in cutting gate structures for Fin Field Effect Transistors (FinFETs) without damaging epitaxy source/drain regions, due to the increasing complexity and miniaturization of semiconductor devices.
Innovation Solution
The use of an etching process that combines anisotropic and isotropic etching techniques to cut gate structures, where the isotropic etching preferentially removes conductive materials over dielectric materials, resulting in a cut opening profile that maintains a greater distance from epitaxy source/drain regions, thereby reducing the risk of damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional etching processes are used to cut gate structures, then the cutting efficiency is maintained, but the epitaxy source/drain regions are at risk of damage due to proximity
Solution Approach 1:
The patent applies parameter changes by transitioning from a conventional single isotropic etching process to a combined anisotropic and isotropic etching process. The anisotropic etching component creates a more vertical cut profile with reduced lateral etching, thereby maintaining a greater distance between the cut opening and the epitaxy source/drain regions. This parameter change in etching behavior resolves the contradiction by enabling efficient cutting while reducing damage risk to sensitive regions.
Solution Approach 2:
The patent employs local quality by creating a cut opening with non-uniform width along its depth - narrower at the top and wider at the bottom. This tapered profile is achieved through the combination of anisotropic and isotropic etching, where the anisotropic component provides vertical precision and the isotropic component provides lateral coverage. The local variation in cut opening width allows the etch to progress efficiently through the gate structure while the narrower upper portion maintains safety margins from adjacent sensitive regions.
2Reliability
If the cut opening is made narrower to avoid damaging epitaxy source/drain regions, then the safety margin is improved, but the etching process time increases
Solution Approach 1:
The patent segments the etching process into two distinct stages: an anisotropic etching stage followed by an isotropic etching stage. The anisotropic stage rapidly removes material vertically to create the main depth of the cut opening, while the isotropic stage refines the profile and creates the tapered geometry. This segmentation allows the process to achieve both narrow safety margins and reasonable process time by optimizing each stage for its specific function rather than using a single conservative etching approach throughout.
Solution Approach 2:
The patent implements periodic action through the sequential application of different etching modes. The process alternates between anisotropic etching (providing vertical precision and speed) and isotropic etching (providing lateral refinement and tapering). This periodic switching between etching modes enables the cut opening to be formed with both the narrow upper portion needed for safety margins and the efficient removal rate needed to minimize process time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient cutting of gate structures while minimizing the risk of damage to epitaxy source/drain regions, thereby increasing the yield of semiconductor devices and expanding the process window for forming conductive features.
Implementation Method 1
an etching process to cut the gate structures. The etching process can include an anisotropic etching and an isotropic etching
Data Source
AI summary
Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.