Standard Cell Gate Cut-Out Routing for Reduced Cell Height
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Solution Overview
Problem
Conventional standard cell designs face challenges in reducing cell height and routing congestion due to gate structures blocking the horizontal extension of source/drain contacts, particularly at advanced technology nodes, complicating signal routing and hindering further cell height reduction.
Innovation Solution
A semiconductor device with a gate structure featuring a cut-out allows a local interconnect to extend through it, enabling horizontal routing without using Mint and/or M1 metal line layers, facilitating reduced cell height by allowing signal routing across gate structures continuously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate structures are used to overlap active regions in conventional standard cell designs, then device density and performance are improved, but routing complexity and congestion increase due to horizontal blockage of S/D contacts
Solution Approach 1:
The patent introduces a new routing dimension by extending the local interconnect vertically through the gate structure via a cut-out, allowing signals to route in three dimensions rather than being constrained to two-dimensional planar routing. This resolves the horizontal blockage problem by providing a vertical path through the gate structure.
Solution Approach 2:
The gate structure is segmented by introducing a cut-out that divides it into portions, creating a vertical pathway through the gate structure. This segmentation allows the local interconnect to pass through the gate structure while maintaining electrical isolation between the source/drain regions on either side.
2Ease of operation
If conventional routing methods using Mint and M1 metal line layers are used to bridge gate structures, then signal routing is achieved, but cell height reduction is hindered due to increased routing congestion
Solution Approach 1:
Instead of using additional metal line layers (Mint, M1) that increase vertical stacking and cell height, the patent routes the local interconnect horizontally through a cut-out in the gate structure at the same vertical level, eliminating the need for additional routing layers and enabling cell height reduction.
Solution Approach 2:
The cut-out in the gate structure acts as an intermediary pathway that mediates the routing of the local interconnect, providing a direct horizontal connection between source/drain regions without requiring additional metal line layers or increasing cell height.
3Reliability
If S/D contacts are disposed between and alongside gate structures, then active device functionality is achieved, but horizontal extension of S/D contacts is blocked by gate structures
Solution Approach 1:
The gate structure is segmented by creating a cut-out, which divides it into separate portions. This segmentation creates a vertical pathway through the gate structure that allows the local interconnect to extend horizontally through the gate structure, effectively bypassing the blockage while maintaining the gate's electrical isolation function.
Solution Approach 2:
The local interconnect is routed through a vertical cut-out in the gate structure, transitioning from two-dimensional planar routing to three-dimensional routing. This allows the interconnect to pass through the gate structure vertically while maintaining horizontal extension, resolving the blockage issue.
Data Source
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AI summary
In an aspect there is provided a semiconductor device comprising: a plurality of circuit cells, each circuit cell comprising: first and second active regions extending in parallel in a first cell direction; at least a first gate structure extending in a second cell direction transverse to the first cell direction to overlap a respective first channel region of each of the first and second active regions, wherein the first gate structure extends continuously between the first and second active regions; wherein the first active region comprises a first S/D region at a first side of the first gate structure, and the semiconductor device further comprises a local interconnect configured to couple the first S/D region to a transistor feature at a second side of the first gate structure opposite the first side, wherein the transistor feature is a second S/D region of the first or second active region, or a second gate structure of the circuit cell, parallel to the first gate structure, wherein the local interconnect comprises a first portion abutting the first S/D region, a second portion abutting the transistor feature, and an intermediate portion extending between the first and second portions through a cut-out formed in the first gate structure.