High-Aspect-Ratio Gate Cuts With Vertical Sidewall Isolation
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in forming high aspect ratio gate cuts with minimal taper, particularly in densely packed transistors, as current methods result in wide trench openings and significant sidewall taper, complicating device isolation and increasing manufacturing costs.
Innovation Solution
A plasma-based etching process is employed to form gate cuts with a high aspect ratio of 5:1 or higher, achieving nearly vertical sidewalls with minimal taper (less than 2 nm) through a series of finely-tuned passivation and etching cycles, using different etch chemistries to maintain verticality and selectivity to dielectric spacers and mask materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form gate cuts, then the gate cuts can be formed, but the trench openings become wide and significant sidewall taper occurs
Solution Approach 1:
The etching process is divided into multiple discrete steps with alternating passivation and etching cycles. Each cycle deposits a thin passivation layer, etches through it, and repeats, creating many small etching increments rather than one large etch. This segmentation allows precise control over the etching front, maintaining vertical sidewalls throughout the deep trench formation.
Solution Approach 2:
The etching process employs periodic alternation between passivation deposition and etching removal. The passivation layer is deposited periodically to protect sidewalls, then periodically removed by etching to advance the trench. This periodic cycle repeats many times, with each cycle contributing a small amount to the final deep vertical trench, preventing cumulative tapering.
2Productivity
If device spacing is reduced to increase transistor density, then more transistors can be packed, but forming isolation structures becomes increasingly challenging
Solution Approach 1:
The solution moves the isolation challenge from the horizontal plane to the vertical dimension by forming deep high aspect ratio trenches (5:1 or higher) that extend vertically through the gate structure. This vertical isolation approach allows dense horizontal packing while maintaining electrical separation through the depth of the structure, enabling high transistor density without compromising isolation effectiveness.
Solution Approach 2:
The process changes the critical parameter from trench width to trench depth and aspect ratio. By forming extremely deep narrow trenches with 5:1 or higher aspect ratios, the isolation effectiveness is maintained through vertical separation rather than horizontal spacing. This parameter transformation allows device spacing reduction while preserving isolation functionality.
3Manufacturing precision
If high aspect ratio gate cuts are formed with minimal taper, then device isolation is improved, but the etching process becomes more complex
Solution Approach 1:
The passivation layer serves a dual function: it protects the trench sidewalls from etching during each cycle, and it self-limits the etch depth to prevent over-etching and tapering. The process is self-regulating, where the deposited passivation material automatically provides the necessary protection without requiring external control mechanisms, simplifying the overall process complexity despite multiple steps.
Solution Approach 2:
The process incorporates feedback through the passivation-etch cycle where each etching step is monitored and controlled by the previously deposited passivation layer. The passivation layer thickness and etch selectivity provide inherent feedback control, ensuring that each cycle removes only the intended amount of material and maintains vertical sidewalls, preventing cumulative errors throughout the multi-cycle process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process enhances device integration density, reduces operational variability, improves material compatibility, and lowers manufacturing costs by 25-35% while ensuring precise and vertical gate cuts for effective transistor isolation.
Implementation Method 1
A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio
Data Source
AI summary
Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.