Gate-Based Decoupling Cells for ECO-Ready IC Layouts
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Solution Overview
Problem
Current integrated circuits face inefficiencies in using spare cells, as they occupy area without direct functional purpose unless needed for metal Engineering Change Orders (ECOs), and conventional decoupling cells are not reconfigurable.
Innovation Solution
Incorporating gate-based decoupling cells in the IC design, which can be reconfigured during ECOs, providing additional capacitance and functional flexibility by replacing conventional spare or filler cells, allowing for increased on-chip capacitance and reduced signal integrity issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If spare cells are added to enable post-manufacturing changes, then adaptability is improved, but area consumption increases
Solution Approach 1:
The decoupling cell is designed with a universal structure that can serve dual purposes: providing decoupling capacitance during normal operation and being reconfigured into functional cells (such as inverters, buffers, or logic gates) when post-manufacturing changes are needed. This multi-functionality eliminates the need for dedicated spare cells, thereby reducing area consumption while maintaining adaptability.
Solution Approach 2:
The invention merges the previously separate functions of decoupling cells and spare cells into a single unified cell structure. By combining the decoupling capacitance function with the potential for functional cell reconfiguration, the design eliminates redundant area consumption while preserving both noise reduction and post-manufacturing adaptability capabilities.
2Reliability
If conventional decoupling cells are used, then signal integrity is improved, but reconfigurability is lost
Solution Approach 1:
The decoupling cell incorporates dynamic reconfigurability through controllable switches (such as transmission gates or MOS transistors) that can change the cell's functionality based on control signals. During normal operation, the cell provides decoupling capacitance for signal integrity; when reconfiguration is needed, the switches are controlled to transform the cell into various functional configurations, thus achieving both signal integrity and adaptability.
Solution Approach 2:
The cell's electrical parameters (such as capacitance, resistance, and connectivity) are made changeable through control signals. By adjusting these parameters dynamically, the cell can transition between providing decoupling capacitance and serving as a functional cell, thereby maintaining signal integrity during normal operation while enabling reconfigurability when needed.
3Ease of manufacture
If filler cells are placed in gaps, then manufacturing efficiency is improved, but functional flexibility is reduced
Solution Approach 1:
The filler cell is designed with a universal structure that maintains manufacturing efficiency through regular pattern alignment while incorporating reconfigurable elements. This allows the filler cell to serve its primary purpose of maintaining manufacturing efficiency and supply rail continuity, while also providing hidden functional capabilities that can be activated through reconfiguration, thus achieving both manufacturing efficiency and functional flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The gate-based decoupling cells enhance IC design flexibility, enabling reconfiguration for various functional cell types, reducing dynamic voltage drops, and increasing stored capacitance without the need for full mask regeneration, thus optimizing area usage and operational performance.
Implementation Method 1
the gate-based decoupling cell comprises at least one diffusion layer for forming a source region and/or a drain region of a transistor, and a polysilicon layer arranged partially over the at least one diffusion layer. The polysilicon layer is electrically conductively connected to a supply line of the gate-based decoupling cell, and the at least one diffusion layer is electrically conductively connected to an opposite supply line
Data Source
AI summary
Disclosed is a method for designing an integrated circuit, wherein the integrated circuit is to be structured in cells, wherein the cells are to comprise functional cells and spare cells. The method comprises: a) designing at least one functional cell; and b) placing a plurality of functional cells on associated pattern positions of an, in particular regular, pattern matrix designed for the functional cells. The method further comprises c) placing, on at least one of the remaining pattern positions of the pattern matrix and instead of at least one spare cell conceivable for the at least one of the remaining pattern positions of the pattern matrix, a gate-based decoupling cell, and alternatively or in addition, d) placing, in at least one gap between pattern positions of the matrix pattern and instead of at least one filler cell conceivable for the at least one gap between pattern positions of the pattern matrix, a gate-based decoupling cell.