Adaptive Gate Drive Delay for Non-Overlapping Transistor Pulses
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Solution Overview
Problem
Existing switching regulator circuits face challenges in preventing overlap of on-time states between high side and low side transistors, which can lead to crowbar currents, reducing efficiency and potentially damaging the transistors, due to delays in drive signals caused by different pathways and varying operating conditions.
Innovation Solution
A circuit with a programmable delay control mechanism that adjusts the delay of drive pulses based on current flow detection, ensuring non-overlap of on-time states between high side and low side transistors without altering the duration of pulses or switching voltage, using a gate drive circuit with initial pulses generated to prevent overlap and adjust delays dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a long dead time is used to prevent overlap of drive signals, then reliability is improved, but productivity deteriorates due to reduced switching efficiency
Solution Approach 1:
The patent implements dynamic adjustment of the dead time period based on detected overlap conditions. The control circuit monitors for crowbar current and adaptively modifies the dead time duration, making it longer when overlap is detected and shorter when no overlap occurs, thereby optimizing both reliability and efficiency under different operating conditions
Solution Approach 2:
The patent employs feedback mechanisms where the control circuit detects the presence of crowbar current and uses this information to adjust the dead time period. This closed-loop control ensures that the dead time is optimized in real-time based on actual circuit conditions, preventing excessive dead time from reducing switching efficiency while maintaining protection against overlap
2Reliability
If switching voltage is altered to prevent overlap, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the overlap detection and control functions into a separate, dedicated control circuit that operates independently from the main power switching path. This modular approach prevents complexity from propagating through the entire circuit while maintaining reliable protection against crowbar current
Solution Approach 2:
The patent introduces an intermediary control circuit that mediates between the drive signals and the power transistors. This intermediary layer detects overlap conditions and adjusts drive signal timing without directly altering the switching voltage or current paths, thereby preventing transistor damage while adding minimal complexity
3Adaptability or versatility
If drive signals pass through different pathways, then adaptability is improved, but manufacturing precision deteriorates due to variable signal delays
Solution Approach 1:
The patent applies preliminary delay adjustment to drive signals based on predicted pathway variations. The control circuit pre-compensates for expected timing differences in different signal pathways, ensuring that signals arrive at the transistors with properly synchronized timing even though they traversed different routes
Solution Approach 2:
The patent dynamically changes the delay parameter of drive signals based on detected overlap conditions and pathway characteristics. By adjusting timing parameters in real-time, the system maintains precise signal synchronization despite signals passing through different pathways with varying inherent delays
Data Source
AI summary
An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.