Gate-Depletion Drain-Extended MOS Transistor for High Voltage Tolerance
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Solution Overview
Problem
CMOS technology faces challenges in increasing transistor gate supply voltage without increasing manufacturing costs or circuit area, as current methods either require high-voltage transistors or thicker gate-oxides, which are undesirable.
Innovation Solution
The use of gate-depletion drain-extended MOS transistors with polysilicon gates having significantly lower doping levels than source and drain regions, allowing for higher gate voltages through depletion layers without adding physical thickness to the gate-oxide, using conventional dual-oxide fabrication processes and modified mask layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-oxide thickness is increased to tolerate higher gate voltages, then gate voltage tolerance increases, but device density and scaling are reduced
Solution Approach 1:
The patent changes the doping parameter of the polysilicon gate from high doping to low doping, which fundamentally alters the electrical characteristics. The low-doped polysilicon gate creates a depletion region that increases the effective gate voltage tolerance without requiring thicker gate-oxide, thus maintaining device density while achieving higher voltage tolerance.
2Reliability
If dedicated high-voltage transistors with additional gate-oxide are used, then gate voltage tolerance increases, but manufacturing cost and cycle time increase
Solution Approach 1:
The patent creates a universal low-doped polysilicon gate structure that can be used across different transistor types (both high-voltage and standard transistors) within the same CMOS process. This single structural modification enables high voltage tolerance without requiring separate high-voltage transistor fabrication processes, thereby reducing manufacturing complexity and cost.
Solution Approach 2:
By changing the doping parameter during the polysilicon gate formation step in the conventional CMOS process, the patent achieves high voltage tolerance using existing manufacturing infrastructure without adding dedicated high-voltage process steps, thus avoiding increased manufacturing cost and cycle time.
3Reliability
If gate-oxide thickness is increased to tolerate higher gate voltages, then gate voltage tolerance increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent modifies an existing process parameter (polysilicon doping level) rather than adding new process steps or structures. This parameter change is integrated into the conventional CMOS fabrication flow, avoiding increases in manufacturing complexity while achieving the desired high voltage tolerance.
4Productivity
If standard polysilicon gate doping levels are used, then transconductance is maintained, but gate voltage tolerance is limited
Solution Approach 1:
The patent identifies that reducing polysilicon gate doping creates a depletion region that simultaneously achieves two objectives: increasing gate voltage tolerance by creating a potential barrier, and maintaining transconductance by preserving the inversion layer formation capability. This parameter optimization resolves the trade-off between voltage tolerance and transconductance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher tolerable gate voltages while maintaining transconductance and reducing manufacturing costs, as it utilizes conventional processes without the need for additional processing steps or increased circuit area.
Implementation Method 1
The lightly doped polysilicon gate creates a depletion layer that enables higher gate voltages to be tolerated
Data Source
AI summary
A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.