Multi-Layer Gate Dielectric for High Capacitance and Channel Mobility
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Solution Overview
Problem
The reduction in size of semiconductor devices leads to performance degradation due to increased remote phonon scattering and decreased channel mobility, as higher dielectric constants in gate dielectric layers enhance capacitance but impair mobility, while lower dielectric constants degrade capacitance and mobility.
Innovation Solution
Incorporating an intermediate dielectric layer with a dielectric constant of 9 or less between the high-k dielectric layer and the 2D semiconductor channel layer, which reduces remote phonon scattering and improves channel mobility, and using a crystalline or amorphous material with grain sizes less than the channel layer to facilitate uniform high-k dielectric layer deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a high-k dielectric layer is used to enhance capacitance, then gate capacitance is improved, but remote phonon scattering increases and channel mobility deteriorates
Solution Approach 1:
The gate dielectric layer is segmented into multiple layers: a high-k dielectric layer (first dielectric layer) for providing high capacitance, and a low-k dielectric layer (second dielectric layer) for reducing remote phonon scattering. This segmentation allows each layer to perform its specific function independently, resolving the contradiction between high capacitance and high mobility.
Solution Approach 2:
Different regions of the gate dielectric structure have different dielectric constants optimized for different functions. The high-k dielectric layer is positioned closer to the channel to maximize capacitance, while the low-k dielectric layer is positioned away from the channel to minimize scattering effects. This local optimization of dielectric properties resolves the contradiction.
2Power
If the dielectric constant is increased to improve capacitance, then gate control is enhanced, but remote phonon scattering increases and mobility decreases
Solution Approach 1:
The gate dielectric is segmented into a high-k layer for gate control and a low-k layer for mobility enhancement, allowing simultaneous optimization of both gate control and carrier mobility through spatial separation of functions.
Solution Approach 2:
The low-k dielectric layer acts as an intermediary between the high-k dielectric layer and the channel, mediating the interaction by providing electrical isolation that reduces remote phonon scattering while allowing the high-k layer to maintain gate control.
3Productivity
If device size is reduced to increase integration density, then productivity is improved, but performance degradation occurs due to short channel effects
Solution Approach 1:
The invention changes the dielectric constant parameter across different layers of the gate dielectric structure. By using a gradient of dielectric constants (high-k near the channel, low-k away from the channel), the device maintains effective gate control in scaled dimensions while minimizing short channel effects and preserving mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances channel mobility by minimizing scattering effects and ensuring uniform high-k dielectric layer deposition, thereby improving the overall performance of semiconductor devices.
Implementation Method 1
The reduction in size of semiconductor devices leads to performance degradation due to increased remote phonon scattering and decreased channel mobility
Implementation Method 2
using a crystalline or amorphous material with grain sizes less than the channel layer to facilitate uniform high-k dielectric layer deposition
Data Source
AI summary
A semiconductor device may include a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional semiconductor material, a gate dielectric layer on a first area of the channel layer, a gate electrode on the gate dielectric layer, and source and drain electrodes in a second area of the channel layer. The gate dielectric layer may include a high-k dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer may be between the high-k dielectric layer and the channel layer. A dielectric constant of the intermediate dielectric layer may be less than a dielectric constant of the high-k dielectric layer.