Multi-Gate Dielectric Fabrication Preventing Dent Regions
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Solution Overview
Problem
Conventional semiconductor device fabrication methods result in the formation of dent regions and reverse narrow width effects due to variations in gate dielectric layer thickness, leading to deteriorated subthreshold characteristics and reliability issues in high-voltage MOS transistors.
Innovation Solution
A method involving the formation of passivation layers with etch selectivity to prevent dent regions, where first and second dielectric layers with specific thicknesses are formed on active regions, and high-k dielectric layers are used to cover exposed surfaces, ensuring uniformity and preventing recesses in the isolation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal oxidation is used to form gate oxide layers, then the gate dielectric layer thickness increases, but dent regions are formed in upper edge regions of the isolation layer
Solution Approach 1:
The patent applies preliminary action by forming a pad oxide layer before the main thermal oxidation process. This pad oxide layer serves as a protective precursor that prevents dent region formation during subsequent processing steps, addressing the shape distortion issue before it occurs in the final gate oxide layer formation.
Solution Approach 2:
The patent introduces an intermediary material layer (nitride layer or oxide-nitride-oxide stack) between the isolation layer and the gate dielectric layer. This intermediary layer acts as a protective barrier that prevents the thermal oxidation process from creating dent regions in the isolation layer upper edge regions, while still allowing the gate dielectric layer to achieve the required thickness.
2Adaptability or versatility
If multiple gate dielectric layers with different thicknesses are formed, then devices with different operating voltages can be created, but subthreshold characteristics deteriorate due to dent regions
Solution Approach 1:
The patent uses an intermediary protective layer (nitride or oxide-nitride-oxide) that enables the formation of multiple gate dielectric layers with different thicknesses while preventing dent region formation. This intermediary layer ensures that the isolation layer maintains its shape integrity, thereby preserving subthreshold characteristics even when creating devices with varying operating voltages.
Solution Approach 2:
The patent applies preliminary protective measures by forming the pad oxide layer and intermediary nitride layer before creating the multiple gate dielectric layers. This preliminary structure prevents the development of dent regions that would otherwise deteriorate subthreshold characteristics, allowing versatile voltage operation without reliability loss.
3Reliability
If the gate dielectric layer thickness is increased for high voltage operation, then breakdown voltage increases, but reverse narrow width effect occurs due to recessed isolation layer
Solution Approach 1:
The patent introduces an intermediary protective layer that prevents the isolation layer from forming recesses during the thermal oxidation process. This ensures that the gate dielectric layer maintains uniform thickness across the active region, even when increased thickness is required for high voltage operation, thereby preventing the reverse narrow width effect while preserving breakdown voltage characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the formation of dent regions and reverse narrow width effects, enhancing the reliability of semiconductor devices by maintaining consistent gate dielectric layer thickness and improving subthreshold characteristics.
Implementation Method 1
forming a passivation layer on the substrate having the isolation layer... A first patterning process is carried out, which etches the passivation layer on the first active region
Implementation Method 2
The semiconductor substrate having the first recessed regions D1 is thermally oxidized to form a first gate oxide layer 25 on each of the exposed first and second active regions 3a and 3b
Implementation Method 3
The pad oxide layer (5 of FIG. 1A) may be etched by a wet etching process to expose the first active region 3a and the second active region 3b
Data Source
AI summary
A method of fabricating a semiconductor device having multiple gate dielectric layers and a semiconductor device fabricated thereby, in which the method includes forming an isolation layer defining first and second active regions in a semiconductor substrate. A passivation layer is formed on the substrate having the isolation layer. A first patterning process is carried out that etches the passivation layer on the first active region to form a first opening exposing the first active region, and a first dielectric layer is formed in the exposed first active region. A second patterning process is carried out, which etches the passivation layer on the second active region to form a second opening exposing the second active region, and a second dielectric layer is formed in the exposed second active region.