Gate Dielectric Doping Through a Diffusion Barrier Layer
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving uniform doping and preventing defects in gate dielectric layers, leading to non-uniformity and increased effective oxide thickness, which affects device performance and efficiency.
Innovation Solution
A method involving the formation of a gate dielectric layer with a diffusion barrier layer and a dopant source layer, where the dopant diffuses through the barrier to create controlled doping at the interface of the high-k dielectric and interfacial layers, preventing mixing and reducing defects, and allowing for precise control of threshold voltage shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doping is performed in scaled-down semiconductor devices, then device performance can be improved, but uniformity of doping becomes difficult to achieve
Solution Approach 1:
The gate dielectric layer is segmented into multiple functional layers: an interfacial layer and a high-k dielectric layer. The dopant source layer is positioned to dope primarily the interfacial layer while minimizing diffusion into the high-k layer, achieving uniform doping control in scaled-down devices through layered segmentation
Solution Approach 2:
Different regions of the gate dielectric layer are given different doping characteristics - the interfacial layer receives dopant concentration optimized for carrier control, while the high-k dielectric layer maintains lower doping to preserve its dielectric properties, creating local quality variations that solve the uniformity problem
2Reliability
If dopant concentration is increased to maintain device performance, then threshold voltage control improves, but effective oxide thickness increases
Solution Approach 1:
The invention changes the physical and chemical parameters of the gate dielectric system by using high-k dielectric materials with higher dielectric constants than traditional SiO2, allowing lower dopant concentrations to achieve the same threshold voltage control while maintaining thinner effective oxide thickness
3Productivity
If doping process is simplified for scalability, then manufacturing efficiency improves, but defect prevention capability decreases
Solution Approach 1:
A dopant source layer is deposited in advance on the gate dielectric before gate electrode formation, establishing controlled doping profiles beforehand. This preliminary action enables subsequent manufacturing steps to proceed efficiently while already having defect-preventing dopant distribution in place
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves a uniform dopant profile with reduced dopant concentration and smaller threshold voltage shifts, enhancing device reliability and performance by maintaining a higher dielectric constant and minimizing effective oxide thickness.
Implementation Method 1
a dopant source layer is formed on the diffusion barrier layer. A dopant of the dopant source layer diffuses into the gate dielectric layer
Data Source
AI summary
The present disclosure describes method to form a semiconductor device having a gate dielectric layer with controlled doping. The method includes forming a gate dielectric layer on a fin structure, forming a diffusion barrier layer on the gate dielectric layer, and forming a dopant source layer on the diffusion barrier layer. The gate dielectric layer includes an interfacial layer on the fin structure and a high-k dielectric layer on the interfacial layer. A dopant of the dopant source layer diffuses into the gate dielectric layer. The method further includes doping a portion of the interfacial layer with the dopant and removing the dopant source layer. The portion of the interfacial layer is adjacent to the high-k dielectric layer.