Gate Dielectric Dipole Boundary Control in Nano-FET Structures
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, challenges arise in efficiently forming and positioning transistors and other electronic components, particularly in nano-FETs, due to issues with dipole overlap and boundary control during manufacturing.
Innovation Solution
The use of doped gate dielectric layers with dipole dopants and simplified masking and dopant drive-in processes allows for better boundary control between device areas, reducing dipole overlap and enabling more compact device placement, applicable to nano-FETs and other transistor types like FinFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but dipole overlap and boundary control issues arise during manufacturing
Solution Approach 1:
The patent divides the gate dielectric layer into multiple segments: a first gate dielectric layer and a second gate dielectric layer with different dipole dopant concentrations. This segmentation allows different regions to have optimized dipole characteristics, preventing dipole overlap issues while maintaining high integration density. The first gate dielectric layer has a first dipole dopant concentration and the second gate dielectric layer has a second dipole dopant concentration, creating distinct functional zones that resolve boundary control problems.
Solution Approach 2:
The patent applies local quality by varying the dipole dopant concentration across different regions of the gate dielectric layer. The first gate dielectric layer and second gate dielectric layer have different local dipole properties tailored to specific device area requirements. This local optimization enables better boundary control between device areas while maintaining high overall integration density, as each region's dipole characteristics are optimized for its specific function.
2Reliability
If dipole dopants are used in gate dielectric layers to control threshold voltage, then device performance is improved, but dipole overlap occurs between adjacent devices
Solution Approach 1:
The gate dielectric layer is segmented into a first gate dielectric layer and a second gate dielectric layer, each with different dipole dopant concentrations. This segmentation creates distinct dipole zones that prevent overlap between adjacent devices. The first dipole dopant concentration in the first gate dielectric layer and the second dipole dopant concentration in the second gate dielectric layer are optimized to provide threshold voltage control without causing dipole overlap issues.
Solution Approach 2:
Different regions of the gate dielectric layer have different local dipole qualities through varying dopant concentrations. The first gate dielectric layer has a first dipole dopant concentration optimized for threshold voltage control, while the second gate dielectric layer has a second dipole dopant concentration that prevents dipole overlap. This local quality variation resolves the harmful dipole overlap effect while maintaining reliable threshold voltage control.
3Manufacturing precision
If complex masking and dopant drive-in processes are used to prevent dipole overlap, then boundary control is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent implements preliminary action by pre-configuring the gate dielectric layer with multiple layers having different dipole dopant concentrations during the deposition process. This preliminary structuring of the gate dielectric layer with optimized dipole characteristics eliminates the need for complex subsequent masking and dopant drive-in processes. The boundary control is achieved through the inherent structure of the multi-layer gate dielectric rather than through complex post-processing steps.
Solution Approach 2:
The patent changes the dipole dopant concentration parameter across different gate dielectric layers to achieve boundary control. By varying the dipole dopant concentration between the first gate dielectric layer and the second gate dielectric layer, the patent optimizes threshold voltage control and prevents dipole overlap without requiring complex masking processes. This parameter variation approach simplifies the manufacturing process while maintaining high manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the manufacturing process by reducing costs and improving the integration density of semiconductor devices by allowing devices to be placed more compactly, thereby improving performance and efficiency.
Implementation Method 1
doped gate dielectric layers with dipole dopants
Implementation Method 2
dopant drive-in processes
Data Source
AI summary
A semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; a second gate dielectric layer disposed over the second channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and the second gate dielectric layer includes a second dipole dopant embedded therein. A boundary between the first gate dielectric layer and the second gate dielectric layer contains the first dipole dopant and the second dipole dopant.