Gate Dielectric Dipole Patterning for FET Threshold Voltage Tuning
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Solution Overview
Problem
The miniaturization of semiconductor devices, such as integrated circuits, poses a challenge in controlling the threshold voltage of transistors, particularly as gate lengths shrink, necessitating methods to form and modulate threshold voltage in different regions of field-effect-transistor (FET) devices effectively.
Innovation Solution
A method involving the deposition of a diffusion barrier layer and a dipole layer over a gate dielectric layer, with varying thicknesses in different regions, followed by an annealing process to drive dipole dopants into the gate dielectric layer, allowing for precise adjustment of threshold voltages in FET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If gate length is reduced to achieve miniaturization, then device density and integration are improved, but control of threshold voltage becomes more difficult
Solution Approach 1:
The patent applies local quality by creating region-specific threshold voltage adjustments through selective dipole layer deposition. Different regions of the gate dielectric receive different concentrations of dipole dopants, enabling localized threshold voltage tuning while maintaining overall device miniaturization. This resolves the contradiction by allowing precise local control without increasing overall device size.
Solution Approach 2:
The patent changes the physical and chemical parameters of the gate dielectric layer by introducing dipole dopants that modify the dielectric's electrical properties. By controlling the concentration and distribution of dipole dopants, the threshold voltage can be precisely adjusted even as gate dimensions are reduced, thereby maintaining manufacturing precision during miniaturization.
2Manufacturing precision
If dipole dopants are driven into gate dielectric layer to adjust threshold voltage, then threshold voltage tuning precision is improved, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-depositing the dipole layer containing dipole dopants before final device assembly. This allows the dipole dopants to be introduced in a controlled manner during the manufacturing process, and subsequent annealing releases them into the gate dielectric layer. This preliminary preparation simplifies the overall process by consolidating multiple steps into a sequential workflow rather than requiring complex in-situ modification techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise tuning of threshold voltages in FET devices, suitable for structures with thin layers, enhancing the performance and flexibility of semiconductor devices by controlling the threshold voltage in various regions.
Implementation Method 1
performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer
Data Source
AI summary
A method of adjusting a threshold voltage in a field-effect-transistor (FET) device includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure, performing a first patterning process to remove a portion of the deposited diffusion layer in the first region, performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region, performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region, and the diffusion barrier layer in the second region and in the third region, and performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer.