Gate Dielectric Dipole Layout for Multiple Nanosheet Threshold Voltages
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Solution Overview
Problem
The semiconductor industry faces challenges in developing nanosheet-based devices with multiple threshold voltages due to space constraints and performance penalties associated with additional material layers required for threshold voltage engineering, particularly in advanced technology nodes where scaling down is hindered by the need for extra material layers that occupy valuable space and affect channel resistance.
Innovation Solution
The method involves forming nanosheet-based transistors with multiple threshold voltages by configuring gate dielectric layers with dipole elements, where dipole layers are deposited and thermally driven into the gate dielectric layer to adjust threshold voltages without requiring additional material layers, allowing for precise tuning of threshold voltages and reducing channel resistance penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional material layers are added for threshold voltage engineering, then multiple threshold voltages can be achieved, but device volume increases and channel resistance increases
Solution Approach 1:
The patent applies local quality by introducing dipole layers with specific orientations at different locations within the gate dielectric structure. Different regions of the gate dielectric contain dipole layers with different orientations (e.g., first dipole orientation in first region, second dipole orientation in second region), creating locally differentiated electrical properties that enable multiple threshold voltages without adding overall device volume.
Solution Approach 2:
The patent transitions from traditional approaches that add material layers in the vertical dimension to embedding dipole layers within the gate dielectric matrix. By configuring dipole orientations in different spatial regions (first region vs. second region) within the same gate dielectric layer thickness, the patent achieves multiple threshold voltages without increasing the vertical stack height or occupying additional device volume.
2Adaptability or versatility
If additional material layers are added for threshold voltage engineering, then multiple threshold voltages can be achieved, but channel resistance increases
Solution Approach 1:
The patent uses local quality by placing dipole layers with different orientations in different regions of the gate dielectric. This creates localized electrical field modifications that independently control threshold voltages for different transistor types (e.g., NFET and PFET) without introducing additional material that would increase channel resistance. The dipole layers are integrated within the existing gate dielectric volume rather than adding separate material layers.
Solution Approach 2:
The patent replaces the mechanical approach of stacking additional material layers with a field-based approach using dipole moments. By configuring dipole orientations (first dipole orientation vs. second dipole orientation) within the gate dielectric, the patent achieves threshold voltage control through electrical field effects rather than physical layer addition, thereby avoiding channel resistance penalties associated with extra material interfaces.
3Productivity
If nanosheet-based devices are scaled down, then production efficiency increases and costs decrease, but gate control becomes more difficult
Solution Approach 1:
The patent applies local quality by introducing dipole layers at specific locations within the gate dielectric structure of nanosheet devices. These locally positioned dipole layers create targeted electrical field enhancements that improve gate control over the channel without requiring increases in gate dielectric thickness or device dimensions. This allows continued scaling of nanosheet devices while maintaining effective gate control.
Solution Approach 2:
The patent changes the electrical parameters of the gate dielectric by incorporating dipole layers with specific orientations. This modifies the effective electric field distribution within the gate dielectric, enhancing gate control without changing the physical dimensions of the device. The dipole orientation parameters (first dipole orientation, second dipole orientation) are tuned to optimize gate control for scaled-down nanosheet structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of transistors with multiple threshold voltages without increasing volume, achieving significant threshold voltage tuning capacity and reducing channel resistance penalties, thus supporting continued downscaling and improving device performance.
Implementation Method 1
dipole layers are deposited and thermally driven into the gate dielectric layer
Data Source
AI summary
A method includes forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, and performing a first thermal drive-in operation at a first temperature to form a diffusion feature in a first portion of the dielectric layer beneath the first patterned layer. The method also includes forming a second patterned layer of a second dipole material, where a first section of the second patterned layer is on the diffusion feature and a second section of the second patterned layer is offset from the diffusion feature. The method further includes performing a second thermal drive-in operation at a second temperature, where the second temperature is less than the first temperature. The method additionally includes forming a gate electrode layer on the dielectric layer.