Gate Dielectric Dipole Tuning for Precise Threshold Voltage

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Solution Overview

Problem

Controlling the threshold voltage of semiconductor devices with gate-all-around structures is challenging due to the limited spacing between channel layers, making it difficult to achieve desired threshold voltages, especially as devices shrink in size.

Innovation Solution

Introduce dipole elements in specific positions within the semiconductor structure to control the threshold voltage by diffusing into the gate dielectric layer, using thermal annealing processes to stabilize the dipole elements and adjust the concentration of impurities in the channel layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the spacing between channel layers is reduced to shrink device size, then device integration density is improved, but threshold voltage control precision deteriorates

Engineering Contradiction:
Improvedevice sizeVSAvoidthreshold voltage control precision
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent introduces dipole layers at specific locations within the gate dielectric structure, creating localized regions with different electrical properties. This allows threshold voltage control to be achieved through localized modifications rather than uniform changes across the entire device, enabling precise control even in highly scaled devices with reduced channel layer spacing.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The dipole layer acts as an intermediary element between the gate electrode and the channel layers. By introducing this intermediate layer with specific dipole moments, the patent mediates the electrical field distribution and enables fine-tuned threshold voltage control without directly modifying the channel layer spacing or geometry.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If dipole elements are introduced to control threshold voltage, then threshold voltage precision is improved, but device structure complexity increases

Engineering Contradiction:
Improvethreshold voltage precisionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The dipole layer is integrated into the existing gate dielectric stack structure, merging the threshold voltage control function with the gate insulation function. This combination approach allows the dipole elements to be incorporated without adding separate, independent structural components, thereby limiting the increase in overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate dielectric layer serves multiple functions: it provides electrical insulation between the gate electrode and channel layers, and simultaneously hosts the dipole layers for threshold voltage control. This multi-functionality reduces the need for additional dedicated structures, thereby limiting complexity increase while achieving precise voltage control.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Achieves precise control of threshold voltage across multiple semiconductor devices, enhancing device performance and reliability by stabilizing the dipole elements and ensuring consistent electrical properties.

Implementation Method 1

controlling the concentration of impurities in the channel layers

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

using thermal annealing processes to stabilize the dipole elements

Methodology Applied
Scientific EffectThermal annealing: Annealing

Data Source

PatentUS20250366002A1Semiconductor device with tunable threshold voltage and method for manufacturing the same
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250366002A1 patent drawing
  • US20250366002A1 patent drawing
  • US20250366002A1 patent drawing

AI summary

A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.