Gate Dielectric Dipoles for Threshold Voltage Tuning in FinFETs
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Solution Overview
Problem
Traditional threshold voltage tuning methods for semiconductor devices, particularly in FinFETs and GAA devices, are insufficient due to continuously shrinking dimensions, leading to increased leakage and adverse effects on equivalent oxide thickness (EOT) and carrier mobility.
Innovation Solution
The use of p-dipole and n-dipole dielectric doping techniques to tune threshold voltages in semiconductor devices, which do not increase dielectric thickness, affect EOT, or carrier mobility, while relaxing design constraints on metal gate work function and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional metal gate work function tuning is used to adjust threshold voltage, then threshold voltage control is achieved, but equivalent oxide thickness increases and carrier mobility deteriorates
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate dielectric layer by introducing dipole-forming dopants (such as aluminum, gallium, or indium) at controlled concentrations. This modifies the electrical properties (threshold voltage) without changing the geometric thickness of the dielectric layer, thereby resolving the contradiction between threshold voltage control and EOT maintenance.
Solution Approach 2:
The patent creates a composite gate dielectric structure by combining the base high-k dielectric material with dipole-forming dopants. This composite approach allows independent optimization of dielectric strength (for low EOT) and electrical tuning (for threshold voltage control), eliminating the trade-off present in traditional metal gate approaches.
2Measurement precision
If metal gate thickness is increased to tune work function, then threshold voltage adjustment is achieved, but device dimensions increase and carrier mobility is affected
Solution Approach 1:
Instead of changing the geometric parameter (gate thickness), the patent changes the electrical parameter (work function) through chemical doping. The dipole-forming dopants modify the electric field distribution and potential profile at the interface, enabling threshold voltage tuning without any increase in physical gate dimensions.
Solution Approach 2:
The patent transitions from controlling threshold voltage through one-dimensional geometric scaling (gate thickness) to controlling it through compositional variation (dopant concentration) in the dielectric layer. This dimensional shift allows independent optimization of both device size and electrical characteristics.
3Measurement precision
If traditional doping methods are used for threshold voltage tuning, then voltage control is achieved, but structural irregularities are introduced
Solution Approach 1:
The patent introduces dipole-forming dopants at specific locations within the gate dielectric structure, particularly near the semiconductor interface, where they can most effectively influence threshold voltage. This localized doping approach achieves precise electrical control while minimizing disruption to the overall crystal structure and reducing structural irregularities compared to bulk doping methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for tunable threshold voltages in FinFETs and GAA devices without increasing dielectric thickness or affecting carrier mobility, thereby improving device performance and reducing structural irregularities.
Implementation Method 1
At least one of the first dopant species and the second dopant species forms a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity.
Data Source
AI summary
A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.