Gate Dielectric Dipoles for Threshold Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in scaling down semiconductor devices like MOSFETs, finFETs, and GAA FETs, which increases manufacturing complexity and makes it difficult to achieve lower and different threshold voltages for FETs, particularly for multi-functional low power portable devices.
Innovation Solution
The solution involves forming NFETs and PFETs with similar WFM layer thicknesses but different threshold voltages on the same substrate by using high-K gate dielectric layers doped with metallic dopants to induce dipoles of different polarities and concentrations, allowing for the adjustment of threshold voltages without varying the WFM layer thicknesses, and incorporating a metallic oxide layer between the high-K gate dielectric and interfacial oxide layers to further tune the work function values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate structures are used in scaled-down semiconductor devices, then manufacturing complexity increases, but achieving lower and different threshold voltages becomes difficult
Solution Approach 1:
The patent changes the chemical composition parameter of the gate dielectric layer by doping it with metallic elements (such as aluminum, gallium, indium) to modify its electrical properties. This allows precise control of threshold voltage through compositional adjustment rather than complex structural changes, resolving the contradiction between manufacturing precision and device complexity
Solution Approach 2:
The patent creates composite gate dielectric materials by combining conventional dielectric materials with metallic dopants. This composite approach enables simultaneous achievement of low threshold voltage and simplified manufacturing, as the metallic dopants provide the necessary electrical tuning without requiring complex multi-layer structures
2Manufacturing precision
If WFM layer thickness is varied to achieve different threshold voltages, then threshold voltage control is improved, but manufacturing cost and time increase
Solution Approach 1:
Instead of changing the physical dimension (thickness) of the WFM layer, the patent changes the chemical composition of the gate dielectric layer by metallic doping. This allows threshold voltage adjustment through compositional parameters rather than dimensional parameters, maintaining manufacturing efficiency while achieving precise voltage control
Solution Approach 2:
The patent uses the same WFM layer thickness for both NFET and PFET devices, copying the dimensional parameter, while achieving different threshold voltages through compositional modification of the gate dielectric. This reduces manufacturing variability and improves productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by 20-30% and time by 15-20%, while enabling the creation of FET gate structures with smaller dimensions and lower threshold voltages, enhancing device performance and efficiency.
Implementation Method 1
using high-K gate dielectric layers doped with metallic dopants to induce dipoles of different polarities and concentrations, allowing for the adjustment of threshold voltages
Implementation Method 2
incorporating a metallic oxide layer between the high-K gate dielectric and interfacial oxide layers to further tune the work function values
Data Source
AI summary
A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.