Gate Dielectric Doping Control for Multi-Vt FinFET Uniformity
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Solution Overview
Problem
The scaling down of semiconductor devices to meet demands for higher storage capacity, faster processing, and lower costs introduces challenges such as non-uniform threshold voltages due to dopant diffusion and compound particle defects, leading to degraded performance and boundary effects between adjacent FETs.
Innovation Solution
A method involving a gate dielectric layer with controlled doping, using a buffer layer to prevent mixing with the high-k dielectric layer and a dopant pulling layer with varying silicon or germanium concentrations to tune threshold voltages, while preventing dopant diffusion across FET boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase storage capacity and processing speed, then device density and performance are improved, but non-uniform threshold voltages and boundary effects between adjacent FETs occur due to dopant diffusion
Solution Approach 1:
The gate dielectric layer is segmented into multiple functional layers: an interfacial layer adjacent to the semiconductor fin, a high-k dielectric layer above the interfacial layer, and a dopant pulling layer above the high-k dielectric layer. This segmentation allows each layer to perform its specific function - the interfacial layer provides good interface characteristics, the high-k dielectric layer provides high capacitance, and the dopant pulling layer selectively removes dopants to prevent boundary effects.
Solution Approach 2:
The dopant pulling layer acts as an intermediary between the dopant source and the gate dielectric structure. It selectively pulls dopants from the high-k dielectric layer through controlled diffusion, preventing dopant accumulation at device boundaries while maintaining uniform doping profiles within devices. This intermediary layer resolves the conflict between achieving sufficient doping for device operation and preventing harmful boundary effects.
2Reliability
If doping is applied to adjust threshold voltage, then device performance is optimized, but compound particle defects and non-uniform dopant distribution occur
Solution Approach 1:
The high-k dielectric layer is deposited over the interfacial layer before dopant introduction, creating a structured gate dielectric stack in advance. This preliminary structuring allows for controlled dopant diffusion into specific regions and enables subsequent selective dopant removal by the dopant pulling layer, preventing compound particle defects that would occur with direct doping of a single-layer dielectric.
Solution Approach 2:
The dopant pulling layer utilizes changes in dopant concentration and diffusion parameters to selectively remove dopants from the high-k dielectric layer. By controlling the composition and thickness of the dopant pulling layer, the doping process parameters are optimized to achieve uniform dopant distribution while preventing harmful effects such as compound particle formation and boundary effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves uniform dopant distribution and reduced threshold voltage shifts, improving device performance by minimizing compound particle defects and boundary effects, enabling the fabrication of multiple threshold voltage FETs with enhanced reliability.
Implementation Method 1
tuning the dopant in the gate dielectric layer by the dopant pulling layer under a thermal condition
Implementation Method 2
doping a portion of the high-k dielectric layer adjacent to the interfacial layer with the dopant
Data Source
AI summary
The present disclosure describes method to form a semiconductor device having a gate dielectric layer with controlled doping and to form multiple devices with different Vt. The method includes forming a gate dielectric layer on a fin structure, forming a buffer layer on the gate dielectric layer, and forming a dopant source layer including a dopant on the buffer layer. The gate dielectric layer includes an interfacial layer on the fin structure and a high-k dielectric layer on the interfacial layer. The method further includes doping a portion of the high-k dielectric layer adjacent to the interfacial layer with the dopant, removing the dopant source layer and the buffer layer, forming a dopant pulling layer on the gate dielectric layer, and tuning the dopant in the gate dielectric layer by the dopant pulling layer.