Gate Dielectric Recess Formation for Uniform Edge Thickness

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Solution Overview

Problem

The uneven thickness of the gate dielectric layer in semiconductor devices, particularly edge thinning, leads to reduced electrical performance, especially in high-voltage transistor devices.

Innovation Solution

A manufacturing method that involves forming a trench in the substrate, creating an isolation structure, and removing the semiconductor layer to form a recess, allowing for a uniform thickness of the gate dielectric layer through processes like etch-back and thermal oxidation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the gate dielectric layer is formed directly on the substrate without removing the semiconductor layer, then the manufacturing process is simpler, but the gate dielectric layer thickness becomes uneven (edge thinning) reducing electrical performance

Engineering Contradiction:
Improvegate dielectric layer thickness uniformityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The semiconductor layer is removed in advance before forming the gate dielectric layer, creating a recess structure that pre-compensates for potential edge thinning. This preliminary action ensures that when the gate dielectric layer is subsequently formed, it deposits on a surface geometry that promotes uniform thickness distribution, thereby resolving the contradiction between thickness uniformity and process simplicity.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the semiconductor layer is removed to form a recess, then the gate dielectric layer thickness uniformity is improved, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvegate dielectric layer thickness uniformityVSAvoidmanufacturing process ease
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The invention changes the geometric parameter of the substrate surface by creating a recess through semiconductor layer removal. This parameter change in surface topology allows the gate dielectric layer to form with uniform thickness, as the recess compensates for the natural tendency toward edge thinning. The parameter change transforms the manufacturing challenge from one of controlling deposition uniformity to one of structured material removal.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the gate dielectric layer is formed with uniform thickness, then the electrical performance is improved, but additional process steps are required

Engineering Contradiction:
Improveelectrical performanceVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By removing the semiconductor layer before gate dielectric formation, the invention creates a preparatory structure that enables uniform dielectric thickness. This preliminary action, while adding a process step, actually simplifies subsequent deposition requirements and improves reliability by preventing edge thinning-related electrical failures, thereby justifying the additional manufacturing step through enhanced device performance.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method ensures a uniform thickness of the gate dielectric layer, thereby enhancing the electrical performance of semiconductor devices.

Implementation Method 1

the method of forming the gate dielectric layer is, for example, a thermal oxidation method

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Data Source

PatentUS20250311385A1Manufacturing method of semiconductor structure
Publication Date: 2025.10.02 POWERCHIP SEMICON MFG CORP
  • US20250311385A1 patent drawing
  • US20250311385A1 patent drawing
  • US20250311385A1 patent drawing

AI summary

A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. A semiconductor layer is formed in the substrate. A portion of the semiconductor layer and a portion of the substrate are removed to form a trench in the substrate. An isolation structure is formed in the trench. After the isolation structure is formed, the semiconductor layer is removed to form a first recess in the substrate. A gate dielectric layer is formed on the substrate exposed by the first recess.