Gate Structure Dielectric Protection to Prevent Gate Height Loss
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Solution Overview
Problem
Existing semiconductor fabrication methods result in gate height loss and difficulties during chemical mechanical polishing due to partial loss of the first mask layer and the use of softer field oxide layers, which complicates the process.
Innovation Solution
A method involving partial removal of the first interlayer dielectric layer to align its top with the first mask layer, followed by forming a second interlayer dielectric layer that covers the mask layer, and subsequent etching to form trenches without damaging the mask layer, thereby preventing gate height loss and simplifying the chemical mechanical polishing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the second mask layer is etched to form openings exposing the gate structure and first interlayer dielectric layer, then the gate cutting process can be performed, but the first mask layer underlying the openings is partially lost, causing gate height reduction
Solution Approach 1:
The patent applies preliminary action by forming a second interlayer dielectric layer that covers and protects the first mask layer before the etching process. This protective layer is prepared in advance to prevent the mask layer from being damaged during subsequent etching operations, thereby maintaining gate height while enabling the gate cutting process to proceed.
Solution Approach 2:
The second interlayer dielectric layer serves as an intermediary protective element between the etching process and the first mask layer. This intermediary layer absorbs the mechanical stress and chemical exposure during etching, preventing direct damage to the mask layer and preserving the gate structure's dimensional integrity.
2Ease of manufacture
If the first interlayer dielectric layer is made of softer field oxide material, then the device structure can be formed, but the CMP process becomes difficult and complex
Solution Approach 1:
The patent applies parameter changes by modifying the material composition and mechanical properties of the second interlayer dielectric layer. This layer is designed with specific hardness and polishing characteristics that are more favorable for CMP processes, thereby reducing process complexity while maintaining the structural benefits of the softer first interlayer dielectric layer.
3Productivity
If the opening is formed to expose the gate structure for cutting, then transistor integration can be increased, but the first mask layer is damaged and gate height is reduced
Solution Approach 1:
The protective second interlayer dielectric layer is formed in advance before the opening etching process. This preliminary protective structure enables the opening to be formed for gate cutting (increasing integration) while simultaneously preventing mask layer damage and maintaining gate height precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents gate height loss and simplifies the chemical mechanical polishing process by protecting the mask layer from damage, while also preventing collapsing of the interlayer dielectric layer and minimizing damage to sources/drains.
Implementation Method 1
forming a second interlayer dielectric layer, which fills up gaps between adjacent portions of the first mask layer and covers the first mask layer
Implementation Method 2
a chemical mechanical polishing (CMP) process is performed thereon so that the other first interlayer dielectric 14 only fills the trenches
Data Source
AI summary
A semiconductor device and method for fabricating the device are disclosed. The method includes: providing a substrate, on which multiple gate structures are formed, a first mask layer formed on tops of the gate structures, and spacers formed on side walls thereof, and a first interlayer dielectric layer formed between adjacent gate structures; partially removing the first interlayer dielectric layer; forming a second interlayer dielectric layer covering the first mask layer; forming a second mask layer and etching it so that at least one opening is formed, which exposes the second interlayer dielectric layer and is aligned with at least a portion of the gate structure and the spacers; partially removing the second interlayer dielectric layer; removing the exposed first mask layer and portions of spacers on both sides thereof; removing the exposed gate structures; and removing the second mask layer and filling it with a third interlayer dielectric layer.