Gate Dielectric Inner Spacer Structure for Scaled MOSFET Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of metal oxide semiconductor field effect transistors (MOSFETs) in semiconductor devices leads to deteriorated operating properties, necessitating improved fabrication methods for enhanced performance.
Innovation Solution
A semiconductor device design featuring vertically stacked semiconductor patterns with a gate dielectric layer and inner spacer structure, including a high-k dielectric layer and inner spacer with specific thicknesses, and a gate electrode configuration that enhances electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density increases, but operating properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D MOSFET structure to three-dimensional vertically stacked semiconductor patterns, enabling multiple channels to be stacked in the vertical direction. This dimensional change allows increased device density without further scaling down the lateral dimensions, thereby maintaining operating properties while improving integration density.
Solution Approach 2:
The patent implements nested structures where gate electrodes and gate dielectric layers surround and encapsulate the vertically stacked semiconductor patterns. The inner spacer is nested within the gate dielectric layer, creating a compact multi-layered configuration that maximizes space utilization and maintains electrical performance at high integration densities.
2Manufacturing precision
If gate dielectric layer thickness is reduced to scale with device size, then capacitance control improves, but leakage current increases
Solution Approach 1:
The patent changes the dielectric constant parameter by employing high-k dielectric materials with dielectric constants significantly higher than traditional silicon dioxide. This allows the gate dielectric layer to maintain adequate thickness for preventing leakage current while achieving the required capacitance control through the high-k material's enhanced dielectric properties.
Solution Approach 2:
The gate dielectric layer is formed as a composite structure combining high-k dielectric materials with other functional dielectric layers. This composite configuration enables simultaneous achievement of low leakage current through the high-k material's thickness maintenance and precise capacitance control through the combined electrical properties of the composite structure.
3Reliability
If inner spacer thickness is increased to improve gate control, then electrical properties improve, but device area increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple semiconductor patterns vertically, allowing the inner spacer to extend in the vertical direction rather than requiring increased horizontal area. This enables improved gate control through increased spacer thickness in the vertical dimension while maintaining compact lateral device footprint.
Solution Approach 2:
The inner spacer is nested within the gate dielectric layer structure, with both components forming a compact vertical stack. This nested configuration allows the inner spacer to achieve sufficient thickness for improved electrical properties while the entire structure remains space-efficient through vertical integration rather than lateral expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves electrical properties and operational efficiency of semiconductor devices by optimizing the gate dielectric layer and spacer structure, allowing for better control over capacitance and stress distribution.
Implementation Method 1
The gate dielectric layer may include a high-k dielectric layer that surrounds the first portion of the gate electrode
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, and a gate dielectric layer between the gate electrode and the semiconductor patterns. An inner spacer of the gate dielectric layer includes a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, a vertical portion between the high-k dielectric layer and the source/drain pattern, and a corner portion between the horizontal portion and the vertical portion. A first thickness of the horizontal portion is less than a second thickness of the vertical portion. The second thickness of the vertical portion is less than a third thickness of the corner portion.