High-Voltage Gate Dielectric Formation Without Mask Layer Removal
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Solution Overview
Problem
High-voltage transistors face issues with breakdown voltage and surface defects due to the use of phosphoric acid in removing nitrogen-containing mask layers during gate dielectric formation, compromising device performance and yield.
Innovation Solution
Forming a semiconductor structure where the nitrogen-containing mask layer is converted into part of the gate dielectric layer, eliminating the need for its removal, thereby enhancing the thickness and reducing surface defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If phosphoric acid is used to remove nitrogen-containing mask layer, then mask layer removal is achieved, but surface defects are generated and device yield decreases
Solution Approach 1:
The patent extracts and removes the nitrogen-containing mask layer entirely from the process by using a deposition technique that does not require mask layer formation, thereby eliminating the need for mask layer removal and avoiding surface defects caused by phosphoric acid
Solution Approach 2:
The patent converts the potentially harmful effect of nitrogen-containing materials by using nitrogen-free deposition techniques, transforming what could be a source of surface defects into a beneficial clean interface that improves device yield
2Ease of manufacture
If phosphoric acid removal process is used, then mask layer is removed, but breakdown voltage decreases due to surface defects
Solution Approach 1:
The patent extracts the problematic phosphoric acid removal step from the manufacturing process by adopting a deposition-based approach that forms the gate dielectric layer without requiring mask layer removal, thereby preserving surface quality and maintaining high breakdown voltage
Solution Approach 2:
The patent converts the potential harm of surface defects into a benefit by using clean deposition techniques that create a defect-free interface, ensuring both ease of manufacture and high breakdown voltage performance
3Ease of manufacture
If mask layer removal is performed, then patterning is completed, but gate dielectric thickness is reduced
Solution Approach 1:
The patent extracts the mask layer removal step entirely by using a deposition process that directly forms the gate dielectric layer with the desired thickness and pattern, eliminating the thickness reduction that occurs during conventional mask removal processes
Solution Approach 2:
The patent performs the patterning action preliminarily through deposition techniques that directly create the final gate dielectric structure with correct thickness and pattern, avoiding subsequent removal steps that would reduce thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method increases the breakdown voltage and extends the lifetime of high-voltage transistors by improving device performance and production yield.
Implementation Method 1
depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer
Data Source
AI summary
A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.