Gate Dielectric Formation for Memory and Transistor Integration
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Solution Overview
Problem
Existing methods struggle to form optimized gate dielectrics for both transistors and memory cells in the same chip, as the requirements for dielectrics differ significantly between these components, leading to implementation challenges.
Innovation Solution
A method is developed to manufacture electronic chips by delimiting active areas for memory cells and transistors, forming a silicon oxide-nitride-oxide tri-layer, depositing a protection layer, and selectively removing portions to form dielectric layers, including a high permittivity layer like hafnium silicate, ensuring independent control over dielectric characteristics for both components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single dielectric formation method is used for both transistors and memory cells, then the manufacturing process is simplified, but the dielectric characteristics cannot be optimized for both component types simultaneously
Solution Approach 1:
The patent segments the dielectric formation process into distinct sequences for memory cells and transistors. Memory cell dielectrics are formed first through deposition of oxide-nitride-oxide layers, followed by transistor dielectric formation through thermal oxidation. This segmentation allows each component type to receive independently optimized dielectric treatment, resolving the contradiction between process simplicity and dielectric optimization.
Solution Approach 2:
The patent applies preliminary action by forming the memory cell dielectric structure before transistor dielectric formation. The oxide-nitride-oxide tri-layer is deposited and patterned first, creating a protective mask that enables subsequent thermal oxidation to form transistor gate oxides without damaging the memory cell dielectrics. This preliminary structuring allows both dielectric types to be optimized independently.
2Manufacturing precision
If different dielectric formation methods are used for transistors and memory cells, then optimized dielectric characteristics are achieved for both components, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple dielectric formation operations into a unified process sequence. The oxide-nitride-oxide deposition serves dual purposes: forming the memory cell dielectric and creating a protective mask for subsequent transistor oxide formation. This merging reduces the total number of separate process steps and aligns with industrial manufacturing workflows, thereby reducing complexity while maintaining dielectric optimization.
Solution Approach 2:
The oxide-nitride-oxide tri-layer acts as an intermediary structure that mediates between the memory cell and transistor formation processes. It serves as both the functional dielectric for memory cells and as a protective mask during transistor dielectric formation. This intermediary role allows the two different dielectric formation methods to coexist without requiring completely separate process flows, thus managing complexity.
3Manufacturing precision
If the protection layer is made thinner, then the manufacturing precision is improved, but the reliability of the protection layer decreases
Solution Approach 1:
The patent employs composite material structure with the oxide-nitride-oxide tri-layer comprising multiple functional sub-layers. The nitride layer provides superior protective properties while the oxide layers provide interface quality and adhesion. This composite structure achieves both thin overall thickness for precision and enhanced reliability through the synergistic properties of different materials working together.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the reliable formation of gate dielectrics for transistors and memory cells with optimized characteristics, improving performance and reliability by maintaining the integrity of dielectric layers and allowing independent control over their properties.
Implementation Method 1
depositing a silicon oxide-nitride-oxide tri-layer
Implementation Method 2
depositing a protection layer
Implementation Method 3
thermally oxidizing the entire surface to form an oxide layer
Implementation Method 4
forming a second layer of a material of high permittivity
Data Source
AI summary
Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.