Gate Dielectric Layering for Threshold Voltage and Mobility Tuning
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in achieving both improved device mobility and precise control over threshold voltage, particularly in nanostructure field-effect transistors (nanostructure-FETs).
Innovation Solution
A two-step process is employed to introduce dipole elements and fluorine atoms into the gate dielectric layer of nanostructure-FETs. This process reduces interference between the dipole elements and fluorine atoms, allowing for independent tuning of threshold voltage and enhancement of device mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dipole elements are introduced into the gate dielectric layer to tune threshold voltage, then threshold voltage control is improved, but device mobility deteriorates due to interference with fluorine atoms
Solution Approach 1:
The gate dielectric layer is segmented into multiple distinct layers: a first gate dielectric layer containing dipole elements for threshold voltage control, and a second gate dielectric layer containing fluorine atoms for mobility enhancement. This segmentation allows each layer to independently perform its specific function without interference between dipole elements and fluorine atoms, thereby resolving the contradiction between threshold voltage control and device mobility.
Solution Approach 2:
Different regions of the gate dielectric structure are assigned different compositions and functions: the first gate dielectric layer is specifically engineered with dipole elements to provide threshold voltage tuning capability, while the second gate dielectric layer is engineered with fluorine atoms to provide mobility enhancement. This local differentiation allows each region to optimize its specific function without compromising the other.
2Quantity of substance
If minimum feature sizes are reduced to improve integration density, then integration density is improved, but device performance deteriorates due to difficulty in achieving both mobility and threshold voltage control
Solution Approach 1:
By segmenting the gate dielectric layer into functionally distinct first and second layers, the invention enables independent optimization of threshold voltage control and mobility enhancement even at reduced feature sizes. This segmentation allows both critical performance parameters to be maintained despite miniaturization, thereby preserving device performance while achieving higher integration density.
Solution Approach 2:
The gate dielectric structure employs composite materials architecture, combining different dielectric materials with specific properties: the first gate dielectric layer uses materials suitable for dipole element incorporation for threshold voltage control, while the second gate dielectric layer uses materials suitable for fluorine atom incorporation for mobility enhancement. This composite approach enables simultaneous achievement of both performance metrics at scaled dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described solution enables nanostructure-FETs to achieve both desired threshold voltages and improved device mobility, addressing the challenges posed by reduced feature sizes.
Implementation Method 1
a first gate dielectric layer comprising dipole elements that tune a threshold voltage of the semiconductor device
Implementation Method 2
a second gate dielectric layer comprising fluorine atoms that improve mobility of the semiconductor device by passivating oxygen vacancy and/or reducing silicon dangling bonds of the gate dielectric layer
Data Source
AI summary
A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.