Gate Dielectric Fabrication Reducing Nitrogen Diffusion

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Solution Overview

Problem

Current manufacturing techniques for ultra-thin gate dielectrics in field effect transistors result in high leakage currents and reduced charge carrier mobility due to nitrogen diffusion at the silicon/gate dielectric interface.

Innovation Solution

A method involving the removal of a native oxide layer, formation of a thermal oxide layer, deposition of a gate dielectric layer, optional nitridization, oxidation, and thermal annealing, all performed in a controlled semiconductor processing system, to fabricate a gate dielectric with reduced nitrogen diffusion and improved carrier mobility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If present manufacturing techniques are used to form ultra-thin gate dielectrics, then the transistor speed increases, but leakage currents increase and charge carrier mobility decreases due to nitrogen diffusion

Engineering Contradiction:
Improvetransistor speedVSAvoidleakage current and charge carrier mobility
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

A thin oxide layer (5-20 Å) is formed on the silicon substrate before depositing the gate dielectric layer. This preliminary oxide layer acts as a barrier to prevent nitrogen diffusion into the silicon substrate during subsequent processing steps, thereby maintaining charge carrier mobility while allowing the use of ultra-thin gate dielectrics for high-speed operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The preliminary oxide layer serves as an intermediary barrier between the silicon substrate and the gate dielectric layer. This intermediate layer prevents direct contact and nitrogen diffusion from the gate dielectric into the silicon, solving the contradiction between achieving ultra-thin dielectric thickness and preventing harmful nitrogen diffusion

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If the gate dielectric thickness is reduced to 20-30 Angstroms or less, then transistor speed increases, but nitrogen diffusion into the silicon/gate dielectric interface increases

Engineering Contradiction:
Improvetransistor speedVSAvoidnitrogen diffusion
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The oxide layer is formed in advance before gate dielectric deposition, creating a protective barrier that prevents nitrogen diffusion even when the gate dielectric is reduced to ultra-thin dimensions of 20-30 Å or less, enabling high-speed operation without the harmful nitrogen diffusion effect

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The method converts the potential harm of nitrogen diffusion into a benefit by using the oxide layer to trap or redirect nitrogen, preventing it from reaching the silicon substrate while still allowing the ultra-thin gate dielectric to function for high-speed performance

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces leakage currents and enhances charge carrier mobility by minimizing nitrogen diffusion and improving the interface reliability between the gate dielectric and silicon substrate.

Implementation Method 1

forming a thermal oxide layer on the silicon substrate

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

oxidizing at least a portion of the gate dielectric layer using an oxygen-containing plasma

Methodology Applied
Scientific EffectPlasma oxidation: Oxidation

Implementation Method 3

thermally annealing the substrate having the thermal oxide layer and the oxidized gate dielectric layer formed thereon

Methodology Applied
Scientific EffectThermal annealing: Annealing

Data Source

PatentUS7888217B2Method for fabricating a gate dielectric of a field effect transistor
Publication Date: 2011.02.15 APPLIED MATERIALS INC
  • US7888217B2 patent drawing
  • US7888217B2 patent drawing
  • US7888217B2 patent drawing

AI summary

A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. Optionally, the gate dielectric layer may be nitridized prior to oxidizing the gate dielectric layer. In one embodiment, at least portions of the method are performed using processing reactors arranged on a cluster tool.