Gate Dielectric Repair in Vertical 3D Memory Access Devices
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Solution Overview
Problem
As design rules shrink, the semiconductor space for fabricating memory devices like DRAM arrays decreases, leading to challenges in forming gate dielectric layers effectively in three-node access devices for vertical three-dimensional memory, resulting in high off-current and gate/drain induced leakage issues.
Innovation Solution
The formation of three-node horizontal access devices without body region contacts, integrating gate dielectric repair to improve gate dielectric quality, and using replacement channels that minimize minority carriers, reducing the need for body potential control and avoiding gas phase doping, thus enhancing drive current and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules are shrunk to increase memory density, then memory capacity is improved, but gate dielectric formation quality deteriorates leading to high off-current and leakage
Solution Approach 1:
The patent performs gate dielectric repair actions before final access device formation. Specifically, a preliminary gate dielectric layer is formed, then selectively removed in access device regions, and subsequently repaired using atomic layer deposition (ALD) to restore dielectric quality before completing the access device structure. This preliminary repair action prevents subsequent leakage issues.
Solution Approach 2:
The patent changes the physical and chemical parameters of the gate dielectric through controlled removal and repair processes. The gate dielectric is selectively removed to expose underlying structures, then repaired by depositing new dielectric material with controlled thickness and composition, transforming the dielectric's physical state and properties to achieve both high-density scaling and low leakage.
2Ease of operation
If conventional access devices with body region contacts are used, then body potential control is achieved, but device complexity and fabrication overhead increase
Solution Approach 1:
The patent extracts and removes the body region contact structure from the access device configuration. By eliminating the body contact and associated body region, the design simplifies the fabrication process and reduces structural complexity while maintaining functionality through alternative gate dielectric repair and control mechanisms.
Solution Approach 2:
The gate structure serves multiple functions: it provides the primary access device control electrode, and through the gate dielectric repair process, it also establishes proper electrical isolation and potential control without requiring a separate body contact structure. The gate dielectric itself becomes the primary control element.
3Productivity
If gas phase doping is used for source/drain formation, then doping efficiency is achieved, but gate dielectric damage and leakage increase
Solution Approach 1:
The patent converts the potentially harmful gas phase doping process into a beneficial selective doping approach. By using plasma-based or ion implantation methods with precise spatial control, the doping process targets only the intended source/drain regions while the gate dielectric repair structure protects adjacent areas, transforming a potentially damaging process into a precise fabrication tool.
Data Source
AI summary
Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material. Selectively removing the sacrificial material in the first region to form first horizontal openings. Repairing a second side of the gate dielectric exposed where the sacrificial material was removed in the first region. Depositing a first source/drain region, a channel region, and a second source/drain region in the first horizontal openings.


