Gate Dielectric Thickness Control via Selective Deglaze
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Solution Overview
Problem
The repeated deglaze process in forming gate dielectric layers for embedded devices, particularly in low voltage logic transistors, leads to a hump phenomenon causing current leakage and device malfunction due to loss of the shallow trench isolation film edge.
Innovation Solution
A method involving selective deglaze processes to form gate dielectric layers with varying thicknesses, where a first deglaze process is performed in one region and subsequent deglaze processes in other regions, preventing excessive loss of the shallow trench isolation film edge, by maintaining specific layers in each region during oxidation and etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a deglaze process is performed repeatedly to form gate dielectric layers with different thicknesses, then the gate dielectric layer thickness is controlled, but the shallow trench isolation film edge is lost causing hump phenomenon
Solution Approach 1:
The patent applies local quality by performing selective deglaze processes on different regions of the substrate. Specifically, a first deglaze process is performed on a first region to form a first gate dielectric layer with first thickness, while a second deglaze process is performed on a second region to form a second gate dielectric layer with second thickness. This regional differentiation allows precise control of gate dielectric thickness in each region without causing hump phenomenon in the shallow trench isolation film edge.
2Adaptability or versatility
If the deglaze process is performed multiple times in different regions, then gate dielectric layers with varying thicknesses are formed, but current leakage occurs due to hump phenomenon
Solution Approach 1:
The patent implements local quality by differentiating the deglaze process across different regions. The first region undergoes a first deglaze process while the second region undergoes a second deglaze process, creating gate dielectric layers with different thicknesses tailored to specific device requirements. This approach enables adaptability for different transistor types (e.g., high voltage vs. low voltage logic transistors) while preventing current leakage by avoiding the hump phenomenon through controlled regional processing.
3Manufacturing precision
If oxidation process is performed repeatedly to form gate dielectric layers, then the required thickness is achieved, but the shallow trench isolation film edge is damaged
Solution Approach 1:
The patent applies local quality by performing selective deglaze operations on different regions after oxidation. The first region is selectively deglazed to form a first gate dielectric layer with first thickness, while the second region is selectively deglazed to form a second gate dielectric layer with second thickness. This regional selectivity allows precise thickness control in each area while preserving the shallow trench isolation film edge strength and preventing damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents the hump phenomenon by ensuring uniformity and accuracy in gate dielectric layer formation, reducing current leakage and enhancing device reliability by maintaining the edge of the shallow trench isolation film.
Implementation Method 1
gate dielectric layers having suitable thicknesses are formed by performing an oxidation process two or three times
Implementation Method 2
repeatedly performing a deglaze process for selectively removing a part of an oxide layer
Data Source
AI summary
A method for forming gate dielectric layers having different thicknesses is provided, The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and the upper oxide layer in a first region, while removing the nitride layer and the upper oxide layer in second, third, and fourth regions; forming the first gate dielectric layer having a first thickness in the second, third, and fourth regions; performing a second deglaze process to the first gate dielectric layer in the third region, thereby forming a second gate dielectric layer having a second thickness; and performing a third deglaze process on the first gate dielectric layer on the fourth region, thereby forming a third gate dielectric layer having a third thickness.