Gate Dielectric Thickness Integration Without Surface Step Height
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Solution Overview
Problem
The existing method for integrating gate dielectric layers of different thicknesses in semiconductor devices results in a step height difference that can lead to over-polishing of high-voltage transistors during chemical mechanical polishing, making it difficult to form an effective gate structure.
Innovation Solution
A manufacturing method that involves forming a first mask layer on the semiconductor substrate, patterning and etching to create a second groove of desired depth, filling and etching back a second material layer to ensure the top surface of the gate dielectric layer is flush with the substrate, and repeating the process to achieve gate dielectric layers of different thicknesses with no step height difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the existing method of forming gate dielectric layers with different thicknesses is used, then high-voltage devices can have thicker gate oxide layers, but a step height difference of 500-1000 Å is created between high-voltage and low-voltage transistor gate oxide layers
Solution Approach 1:
The patent applies preliminary action by forming a fill material layer in the opened region before forming the gate dielectric layer. This fill material layer serves as a preliminary structure that enables subsequent etching to create the groove of precise depth, allowing the gate dielectric layer to be formed at the correct thickness without creating excessive step height differences.
Solution Approach 2:
The patent inverts the conventional approach by instead of forming the gate dielectric layer directly and then removing excess, it first forms a thick fill material layer, then etches back to create a groove of the precise depth needed, and finally forms the gate dielectric layer to fill the groove. This inversion allows precise control of the gate dielectric thickness while eliminating step height differences.
2Reliability
If a thicker gate oxide layer is formed for high-voltage devices, then the device can operate at higher voltages, but the top surface of the gate oxide layer becomes higher than the substrate surface by a predetermined distance
Solution Approach 1:
The patent forms a fill material layer as a preliminary structure that extends above the substrate surface, then etches it back to create a groove of the precise depth needed for the gate dielectric layer. This preliminary action allows the gate dielectric layer to be formed at the correct thickness for high-voltage operation while ensuring its top surface is flush with the substrate surface.
Solution Approach 2:
The patent changes the parameter of the gate dielectric layer formation process by using a groove etching approach instead of direct deposition. By controlling the groove depth parameter and then filling it with gate dielectric material, the method achieves the precise thickness needed for high-voltage operation while maintaining the top surface at the substrate level.
3Ease of manufacture
If the step height difference between gate oxide layers is reduced or eliminated, then proper gate formation can be achieved, but additional process steps including forming fill material layers and etching grooves are required
Solution Approach 1:
The patent merges multiple functions into the fill material layer: it serves as a placeholder to define the gate dielectric layer region, as a material to be etched back to create the groove of precise depth, and as a template for subsequent gate dielectric layer formation. This merging of functions allows the method to achieve precise gate dielectric thickness control and eliminate step height differences through a integrated process sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the top surfaces of gate dielectric layers of different thicknesses to be flush, facilitating proper gate formation and preventing defects in high-voltage devices by eliminating the step height difference, thus enabling effective gate structure formation.
Implementation Method 1
The opened region is obtained by means of coating, exposing, and developing with a photoresist
Implementation Method 2
an oxide film is then formed in the high-voltage region by means of diffusion
Data Source
AI summary
The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer.