Gate Dielectric Layer Thickness Variation Control
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving stable threshold voltage for I/O devices due to thickness variations of the gate dielectric layer, particularly as transistor sizes shrink, leading to device instability and potential failure.
Innovation Solution
A method involving the formation of a semiconductor device with a gate dielectric layer comprising a thicker interfacial layer and a high-k dielectric, along with a fluorine-containing plasma treatment, to reduce thickness variations and enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the thickness of the gate dielectric layer is reduced to maintain performance with decreased gate length, then device performance is improved, but thickness variations cause shifts in threshold voltage leading to device instability
Solution Approach 1:
The gate dielectric layer is segmented into multiple distinct layers: a first gate dielectric layer (interfacial layer) and a second gate dielectric layer (high-k dielectric). This segmentation allows each layer to serve specific functions - the interfacial layer provides a stable base with controlled thickness, while the high-k layer provides the necessary electrical performance, thereby resolving the contradiction between performance and threshold voltage stability.
Solution Approach 2:
The gate dielectric structure uses composite materials by combining different dielectric materials with different properties. The interfacial layer typically uses silicon oxide or silicon oxynitride, while the second layer uses high-k dielectric materials such as hafnium oxide, tantalum oxide, or aluminum oxide. This composite structure enables both thin effective thickness for performance and controlled physical thickness for stability.
2Object-generated harmful factors
If high-k gate dielectrics are used to reduce gate leakage, then gate leakage is reduced, but thickness variations of the gate dielectric layer still cause threshold voltage shifts
Solution Approach 1:
By segmenting the gate dielectric into an interfacial layer and a high-k layer, the patent ensures that the high-k layer thickness is controlled independently. The interfacial layer thickness is optimized for interface quality, while the high-k layer thickness is precisely controlled to achieve desired electrical characteristics without excessive variation, thus reducing both gate leakage and threshold voltage shifts.
Solution Approach 2:
The patent changes the physical and electrical parameters of the gate dielectric structure by using materials with different dielectric constants. The high-k dielectric material has a dielectric constant significantly higher than silicon oxide, allowing for thicker physical layers that provide better leakage control while maintaining equivalent electrical thickness, thereby reducing both gate leakage and sensitivity to thickness variations.
3Productivity
If the gate length and spacing between devices are decreased to increase circuit density, then circuit integration is improved, but thickness variations are exacerbated leading to device instability
Solution Approach 1:
The segmented gate dielectric structure allows for better control of thickness variations even as gate length decreases. The interfacial layer provides a consistent base thickness, while the high-k layer can be precisely deposited to achieve uniform electrical characteristics across the wafer, compensating for the reduced tolerance margins imposed by smaller device dimensions.
Solution Approach 2:
The composite gate dielectric structure using high-k materials enables scaling to smaller dimensions while maintaining device stability. The high-k materials provide superior electrical control that compensates for the reduced physical dimensions, allowing higher circuit density without proportionally increasing device instability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the threshold voltage and reduces device instability by minimizing thickness variations of the gate dielectric layer, thereby improving the performance and reliability of semiconductor devices.
Implementation Method 1
performing a fluorine-containing plasma treatment on the high-k dielectric and interfacial layer
Data Source
AI summary
A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer. An entirety of a top surface of the first interfacial layer is a curved convex surface. Furthermore, the method includes forming a first high-k dielectric over the first interfacial layer. Additionally, the method includes forming a first gate electrode over a first portion of the first high-k dielectric and surrounded by a second portion of the first high-k dielectric.